Digital Design Manager - Toronto, Ontario, Canada
$198,000 CAD yearly
Originally posted 15 September 2026 by the employer — open 0 days.
About the role
This role will lead day-to-day DFT architecture and execution for Astera Labs' signal-conditioning products, helping deliver highly testable, high-quality silicon for rack-scale AI infrastructure.
What you'll do
- Define DFT plans for signal-conditioning products supporting high-speed PCIe and Ethernet connectivity and advanced multi-die packaging configurations.
- Drive scan insertion, ATPG, compression, MBIST, LBIST, JTAG/IJTAG, and high-speed SerDes BIST requirements.
- Collaborate with product, manufacturing, assembly, and test engineering on yield learning, failure analysis, and root-cause resolution.
- Develop pre-bond, post-bond, and package-level test approaches for known-good-die screening and advanced packaging.
- Mentor DFT engineers and coordinate execution across product development milestones.
- Partner with OSATs, ATE vendors, packaging partners, and internal stakeholders to resolve technical issues and maintain schedules.
What you'll need
- Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related field.
- 10-15 years of experience in Digital Design engineering or related semiconductor design and test work.
- Hands-on experience with scan, ATPG, compression, MBIST, LBIST, JTAG, and/or IJTAG methodologies.
- Understanding of the ASIC design flow from RTL through GDS and DFT signoff.
- Experience with DFT EDA tools such as Synopsys DFT Compiler, TetraMAX, DFTMAX, Siemens Tessent, or equivalent.
- Understanding of high-speed signal conditioning, SerDes physical-layer behavior, signal integrity, die-to-die connectivity, or advanced packaging test requirements.
Nice to have
- Master’s or PhD in Electrical Engineering, Computer Engineering, or a related field.
- Experience with 2.5D or 3D integration, silicon interposers, TSVs, hybrid bonding, micro-bumps, chiplets, or known-good-die strategies.
- Knowledge of IEEE 1838, IEEE 1149.1, IEEE 1687, and relevant JEDEC standards for multi-die testing.
- Experience with PCIe, Ethernet, UALink, and high-speed SerDes physical-layer validation or test.
- Familiarity with ATE platforms, wafer probe, OSAT engagement, production test economics, and yield analysis.
This role has been open 0 days — well below the 64-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
946
|
Median days open
64 d
|
Median salary
$182k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (946 roles · 100 employers) |
|---|---|---|
| Open roles in this specialty | 22 | 946 |
| Open roles in the wider Digital Design & Verification family | 51 | 3096 · 115 employers |
| Median days open | 41 d | 64 d (−23 d vs this employer) |
| Median salary (USD postings) | — | $182k |
Who's hiring in this category
- Qualcomm · 137 open roles · median 54 d
- AMD · 58 open roles · median 68 d
- NXP Semiconductors · 51 open roles · median 67 d
- Synopsys · 50 open roles · median 30 d
- NVIDIA · 48 open roles · median 49 d
- Marvell Technology · 41 open roles · median 120 d
How we counted: 946 open Digital/RTL Design (RTL Design) roles from 100 employers tracked in the SemiconductorJobs index, counted 15 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.