Digital Design Engineer - Chandler, AZ, United States

Originally posted 24 September 2026 by the employer.

This role focuses on digital control logic for mobile phone LNAs, TX controllers, and switches.

About the role

This role involves the Verilog design of digital control logic for mobile phone LNAs, TX controllers, and switches. The scope includes RTL-to-GDS flow, area optimization, DRC/LVS error resolution, and physical design.

What you'll do

• Perform Verilog design of digital control logic.
• Conduct design and timing closure using Cadence Innovus.
• Manage RTL-to-GDS flow, area optimization, and DRC/LVS error resolution.
• Execute digital synthesis using Cadence Genus or Synopsys Design Compiler.
• Perform verification on Verilog code using simulation tools.
• Develop script automation with Python to aid in mobile designs.

What you'll need

• Master’s degree in Electrical Engineering and 6 months of experience, an internship, co-op, or 6 graduate credit hours.
• Knowledge of design and timing closure (TCL layout setup script generation, setup/hold/width timing violation fixing) using Cadence Innovus.
• Experience with RTL-to-GDS flow, area optimization, and DRC/LVS error resolution.
• Proficiency in digital synthesis using Cadence Genus or Synopsys Design Compiler and timing constraint generation in TCL.
• Expertise in Verilog digital design and verification and understanding of Verilog/System Verilog syntax.
• Understanding of verification test benches, clocking, and auto-checking.
• Ability to perform verification on Verilog code using simulation tools.
• Experience with Python scripting and other scripting languages.