Digital Design Engineer
$115,600 - $173,400 USD yearly
Originally posted 24 June 2026 by the employer. Relisted by the employer on 15 October 2026.
About the role
The Digital Design Engineer is responsible for designing, developing RTL, and implementing digital IPs serving systems that connect SoC to DRAM devices and provide high-speed links in multi-die systems. The role focuses on DDR and die-2-die interfaces across high-speed compute and server domains.
What you'll do
- Architect, design, and implement digital IPs, control logic, and data-path blocks for DDR and die-2-die parallel interfaces. - Work closely with systems architecture, verification, timing, and physical design engineers to deliver SoC interface solutions. - Drive ASIC front-end implementation flows including logic synthesis, linting checks, and clock domain crossing analysis. - Execute low-power implementation and sign-off alongside gate level simulation debug. - Collaborate with cross-functional engineering teams to support all phases of implementation and silicon bring up.
What you'll need
- Bachelor's degree in Science, Engineering, or a related field. - Minimum 4 years of ASIC design, verification, or related work experience. - Experience in ASIC design, verification, validation, integration, or related engineering workflows.
Nice to have
- Master's degree with 2+ years or Bachelor's degree with 4+ years of relevant work experience. - Hands-on experience with high-speed, low-power digital logic design, ASIC front-end implementation tool flows, and silicon bring up. - Expertise in digital IP design using System Verilog, logic synthesis, linting checks, clock domain crossing best practices, and low-power sign off. - Experience with Design for Test (DFT) flows for stuck-at and TDF modes, as well as gate level simulation bring up and debug. - Prior experience with high-speed parallel physical interface designs and low power designs.
This role has been open 119 days — well above the 62-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1070
|
Median days open
62 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (1070 roles · 105 employers) |
|---|---|---|
| Open roles in this specialty | 157 | 1070 |
| Open roles in the wider Digital Design & Verification family | 413 | 3298 · 115 employers |
| Median days open | 58 d | 62 d (−4 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Who's hiring in this category
- Qualcomm (this employer) · 153 open roles · median 58 d
- Synopsys · 87 open roles · median 35 d
- AMD · 76 open roles · median 40 d
- Analog Devices · 49 open roles · median 51 d
- NXP Semiconductors · 42 open roles · median 90 d
- NVIDIA · 41 open roles · median 62 d
How we counted: 1070 open Digital/RTL Design (RTL Design) roles from 105 employers tracked in the SemiconductorJobs index, counted 22 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.