Digital CAD DFT Methodology, Sr Architect-19503

Drive advanced test access networks and methodology deployments using Synopsys TestMAX DFT and TestMAX ATPG.

Originally posted 4 November 2026 by the employer.

About the role

As a Digital CAD DFT Methodology, Sr Architect, you will drive advanced DFT methodologies and serve as a technical expert for Synopsys TestMAX DFT, ATPG, diagnosis, and silicon lifecycle solutions across complex ASIC and SoC programs. You will join the Digital Methodology Center of Excellence to define test access infrastructures, deployment strategies, and signoff criteria.

What you'll do

• Lead the deployment of advanced DFT architectures, including scan compression, hierarchical DFT, boundary scan, IEEE 1500 wrapper solutions, IJTAG infrastructures, and embedded test technologies.
• Architect scalable test access and instrumentation networks utilizing IEEE 1149.1, IEEE 1149.6, IEEE 1687, and IEEE 1500 standards.
• Develop best practices for DFT insertion, ATPG generation, pattern validation, diagnosis, and coverage optimization.
• Drive reusable methodologies, automation, and signoff criteria to enhance deployment quality and engineering efficiency.
• Partner with R&D teams to influence product capabilities and support strategic customer engagements, methodology reviews, and technical escalations.
• Mentor engineers and build DFT expertise across the organization.

What you'll need

• BS or MS in Electrical Engineering, Computer Engineering, or a related field.
• 18+ years of experience in the semiconductor or EDA industry, with deep experience in DFT, ATPG, and manufacturing test methodologies.
• Hands-on experience with Synopsys TestMAX DFT and TestMAX ATPG solutions.
• Demonstrated expertise architecting and implementing DFT solutions for large-scale ASIC and SoC designs, including scan insertion, scan compression, hierarchical DFT, diagnosis, coverage optimization, and test cost reduction.
• Expertise with IEEE standards including IEEE 1149.1, IEEE 1149.6, IEEE 1687, and IEEE 1500, as well as JTAG/TAP architectures, boundary scan, IJTAG instrumentation networks, and embedded instrument access solutions.
• Experience integrating DFT IP including embedded compression, OCC, LBIST, TAP controllers, JTAG/IJTAG infrastructure, TDR networks, and IEEE 1500 wrappers.
• Strong understanding of RTL-to-GDSII implementation flows and the interaction between DFT, synthesis, physical design, timing closure, and signoff.
• Proficiency in Tcl, Python, Perl, Shell, or similar scripting languages for methodology development and automation.

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