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Qualcomm

Digital ASIC Design Engineer

Qualcomm San Diego, California, United States of America, United States 2 months ago
Digital Design & SoC Architecture

$98,500 - $147,700 USD yearly

Originally posted 17 August 2026 by the employer.

About the role

This role is for a Digital ASIC Design Engineer responsible for defining, modeling, designing, optimizing, verifying, validating, implementing, and documenting IP development for various high-performance, low-power products.

What you'll do

  • Use tools and applications to execute the architecture and design of SOC according to design protocol.
  • Resolve architecture, design, or verification problems by applying sound ASIC engineering practices.
  • Execute the design and support verification efforts of ASICs, SoC, and IP cores with focus on clock/power related features.
  • Participate in the design and analyses of IPs.
  • Identify areas for flow and process improvements.
  • Provide feedback on silicon learnings to improve design methodology, IP, and SoC design.

What you'll need

  • Bachelor's degree in Science, Engineering, or a related field.
  • RTL design experience with Verilog/System Verilog.
  • Proficiency in an automation/scripting language such as Python or Perl.

Nice to have

  • Master's degree in Electrical Engineering, Computer Science, or Computer Engineering.
  • Six months of relevant experience in ASIC design, scripting, and architecture.
  • Specific experience in clock design of ASIC/SoC.

Skills: RTL Design, Verilog/System Verilog, ASIC, SoC, logic design

Market context

This role has been open 60 days — below the 61-day median for Digital/RTL Design roles.

Digital/RTL Design · RTL Design

Open roles in category
1024
Median days open
61 d
Median salary
$185k
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
How Qualcomm compares in Digital/RTL Design hiring
Metric Qualcomm All employers we track in this specialty (1024 roles · 103 employers)
Open roles in this specialty 140 1024
Open roles in the wider Digital Design & Verification family 383 3198 · 115 employers
Median days open 62 d 61 d (+1 d vs this employer)
Median salary (USD postings) — $185k

Skills observed across this category: RTL Design, Verilog/System Verilog, ASIC, SoC, logic design

Who's hiring in this category

  • Qualcomm (this employer) · 140 open roles · median 63 d
  • Synopsys · 86 open roles · median 31 d
  • AMD · 71 open roles · median 37 d
  • Analog Devices · 47 open roles · median 49 d
  • NVIDIA · 44 open roles · median 59 d
  • NXP Semiconductors · 42 open roles · median 85 d

How we counted: 1024 open Digital/RTL Design (RTL Design) roles from 103 employers tracked in the SemiconductorJobs index, counted 17 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.

Apply now
San Diego, California, United States of America, United States
On-site
$98,500 - $147,700 USD yearly
2 months ago

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