DFT Staff Engineer - Noida, Uttar Pradesh, India
Originally posted 18 September 2026 by the employer — open 0 days.
About the role
This role involves defining, modeling, designing, optimizing, verifying, validating, implementing, and documenting IP development for high-performance, high-quality, low-power products.
What you'll do
- Define, model, design, optimize, verify, validate, implement, and document IP (block/SoC) development.
- Apply in-depth knowledge of DFT concepts.
- Perform scan insertion, ATPG, and coverage analysis.
- Analyze Transition delay test coverage.
- Define test mode timing constraints and provide timing fixes for violations.
- Simulate test vectors.
What you'll need
- Bachelor's degree in Science, Engineering, or related field and 4+ years of ASIC design, verification, validation, integration, or related work experience, OR Master's degree in Science, Engineering, or related field and 3+ years of ASIC design, verification, validation, integration, or related work experience, OR PhD in Science, Engineering, or related field and 2+ years of ASIC design, verification, validation, integration, or related work experience.
- 8 years experience in ASIC/DFT.
- In-depth knowledge of DFT concepts.
- Hands-on experience in scan insertion, ATPG, coverage analysis, and Transition delay test coverage analysis.
- Expertise in test mode timing constraints definition and providing timing fixes/corrective actions for timing violations.
- Expertise in scripting languages such as Perl, Shell, etc.
- Experience in simulating test vectors.
- Knowledge of equivalence check, DFT DRC rules in RTL lint tools (like Spyglass) and ATPG tools (like TK, TetraMax).
Nice to have
- Working experience in Synopsys TetraMax/DFTMax and Cadence Encounter Test.
This role has been open 0 days — well below the 65-day median for DFT Engineering roles.
DFT Engineering · DFT Test
|
Open roles in category
214
|
Median days open
65 d
|
Median salary
$200k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (214 roles · 50 employers) |
|---|---|---|
| Open roles in this specialty | 25 | 214 |
| Open roles in the wider Digital Design & Verification family | 381 | 3022 · 114 employers |
| Median days open | 77 d | 65 d (+12 d vs this employer) |
| Median salary (USD postings) | — | $200k |
Who's hiring in this category
- AMD · 33 open roles · median 44 d
- Qualcomm (this employer) · 22 open roles · median 77 d
- NVIDIA · 19 open roles · median 66 d
- NXP Semiconductors · 17 open roles · median 70 d
- Micron Technology · 10 open roles · median 109 d
- Intel Corporation · 8 open roles · median 49 d
How we counted: 214 open DFT Engineering (DFT Test) roles from 50 employers tracked in the SemiconductorJobs index, counted 18 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.