DFT Lead Engineer - USA-CA San Jose Innovation Drive, United States
$143,800 USD yearly
Originally posted 11 August 2026 by the employer.
This role focuses on solving testability problems in 7nm and beyond.
About the role
This role is responsible for leading DFT programs from chip-level specification, through implementation and verification, to successfully releasing products to production. The position involves working on SoC DFT activities for Broadcom APD designs, including DFT Architecture, test insertion and verification, pattern generation, coverage improvement, and post-silicon debug and yield improvement for 7nm processes and beyond.
What you'll do
- Define appropriate DFT specifications for ASICs based on feature requirements and DPPM goals.
- Implement DFT, including Scan, MBIST, TAP, LBIST, IO, SerDes, and other I/P DFT integration.
- Generate, verify, and debug test vectors before tape release.
- Validate and debug test vectors on ATE during silicon bring-up.
- Assist with silicon failure analysis, diagnostics, and yield improvement efforts.
- Interface with customers, physical design, and test engineering/manufacturing teams.
What you'll need
- Strong DFT background including IO and Analog DFT, ATPG, Scan, and BIST.
- Experience with Scan Insertion and scan compression using DFT Compiler or Mentor TestKompress.
- Proficiency in ATPG vector generation, simulation, and debugging with TetraMax or Fastscan.
- Experience in Verilog coding, testbench generation, and simulation.
- Memory BIST insertion and verification experience on embedded SRAM, CAM, eDRAM, and ROM.
- Knowledge of IEEE1149.1 and IEEE1149.6 for Boundary Scan Verification and test vector generation.
- Understanding of Test-STA and constraints, IEE1687, IJTAG, ICL, and PDL.
- Solid knowledge in analog and digital circuit design, device physics fundamentals, Si processing, logical and physical synthesis, and transistor reliability principles.
- Ability to code using TCL, PERL, RUBY, PYTHON, or C++.
Nice to have
- Experience working on the ATE.
- Experience with Serdes, DDR, PCIE, ENET, CXL IOBIST verification and silicon debug.
- Experience working on Tessent SSN.
This role has been open 67 days — well above the 57-day median for DFT Engineering roles.
DFT Engineering · DFT Test
|
Open roles in category
242
|
Median days open
57 d
|
Median salary
$203k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Broadcom | All employers we track in this specialty (242 roles · 53 employers) |
|---|---|---|
| Open roles in this specialty | 7 | 242 |
| Open roles in the wider Digital Design & Verification family | 50 | 3202 · 115 employers |
| Median days open | 96 d | 57 d (+39 d vs this employer) |
| Median salary (USD postings) | — | $203k |
Who's hiring in this category
- AMD · 39 open roles · median 43 d
- NVIDIA · 23 open roles · median 35 d
- Qualcomm · 23 open roles · median 100 d
- NXP Semiconductors · 18 open roles · median 65 d
- Synopsys · 14 open roles · median 24 d
- Micron Technology · 10 open roles · median 64 d
How we counted: 242 open DFT Engineering (DFT Test) roles from 53 employers tracked in the SemiconductorJobs index, counted 17 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.