Lead the test architecture for high-speed parallel optical links utilizing arrays of microLED transmitters and photodetector receivers.
About the role
As DFT Lead at Avicena, you will own the test architecture of a mixed-signal ASIC from scan and BIST through analog test access and production test delivery. The role supports optical links built from arrays of microLED transmitters and photodetector receivers.
What you'll do
- Own the DFT architecture and strategy for a mixed-signal ASIC, including coverage and test-time targets.
- Implement scan insertion and compression, and generate ATPG patterns for stuck-at, transition, and path-delay faults.
- Implement memory BIST and repair, and IEEE 1149.1/1687 access for test and instrument control.
- Define link-level test features including loopback modes, PRBS generators and checkers, and analog observability and trim access.
- Verify DFT logic and patterns with gate-level simulation, and close test-mode timing with the implementation team.
- Deliver ATE patterns and support tester bring-up, silicon failure diagnosis, yield learning, and test-time reduction.
What you'll need
- BS or MS in Electrical or Computer Engineering with 10+ years of DFT experience on production ASICs.
- Hands-on expertise with Siemens Tessent or Synopsys TestMAX/DFTMAX/TetraMAX.
- Experience with scan compression, ATPG, memory BIST, and JTAG/IJTAG.
- Experience with gate-level simulation of test patterns and test-mode timing closure.
- Experience with ATE bring-up and silicon failure diagnosis.
Nice to have
- DFT for mixed-signal chips with analog test access.
- Test of high-speed I/O, including loopback, PRBS and margining; IEEE 1149.6.
- Hierarchical DFT.
- Yield analysis and diagnosis tools.
- Experience leading DFT engineers.
More semiconductor jobs: DFT engineer jobs · Sunnyvale jobs
First seen in our index 7 days ago, well below the 55-day median for DFT Engineering roles.
DFT Engineering · DFT Test
|
Open roles in category
301
|
Median days since first seen
55 d
|
Category median salary (all employers)
$206k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Avicena | All employers we track in this specialty (301 roles · 55 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 301 |
| Open roles in the wider Digital Design & Verification family | 2 | 3499 · 119 employers |
| Median days since first seen | 7 d | 55 d (+48 d vs this employer) |
| Median salary (USD postings) | n/a | $206k |
Who's hiring in this category
- AMD · 43 open roles · median 49 d
- Broadcom · 29 open roles · median 8 d
- NVIDIA · 24 open roles · median 51 d
- Qualcomm · 24 open roles · median 81 d
- NXP Semiconductors · 19 open roles · median 65 d
- Synopsys · 19 open roles · median 35 d
How we counted: 301 open DFT Engineering (DFT Test) roles from 55 employers tracked in the SemiconductorJobs index, counted 11 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there, and is counted in the wider Digital Design & Verification family row. Days are counted from when our index first saw each posting, not from the employer's original posting date.