DFT Implementation Engineer - Texas, Austin, United States
$141,910 - $200,340 USD yearly
Originally posted 21 July 2026 by the employer.
About the role
As a DFT Implementation Engineer at Intel Corporation, you will integrate Design for Test capabilities into SoC and IP solutions. You will collaborate across architecture, design, verification, and manufacturing teams to optimize power, performance, area, and test coverage.
What you'll do
- Develop logic design and register transfer level (RTL) coding to support DFT features including SCAN, MBIST, and BSCAN. - Provide timing closure support and test content generation for manufacturing. - Collaborate in defining architecture and microarchitecture features for blocks, subsystems, and SoCs under DFT. - Write, integrate, and verify RTL and structural code for DFT functionality to meet architecture specifications. - Support IP and SoC integration to ensure high-quality implementation of DFT blocks. - Develop high-volume manufacturing (HVM) content for rapid bring-up and production on automatic test equipment (ATE), and verify features on silicon.
What you'll need
- Bachelor's degree in Electrical Engineering, Computer Engineering, or a related field. - 5+ years of experience in DFT, SoC design, or related semiconductor design areas. - Experience with Tessent Shell flows and SSN methodology. - Hands-on experience with ATPG, scan insertion, and/or MBIST/repair. - RTL design experience using hardware description languages such as Verilog, VHDL, or SystemVerilog.
Nice to have
- Experience with Tessent Fast IO, ISTK, and related methodologies. - Familiarity with industry standards such as IEEE 1687 (IJTAG), IEEE 1149.1 (JTAG), IEEE 1500 (Core Test), and IEEE 1838. - Experience with industry-standard DFT tools including Siemens EDA (Mentor) Tessent, Synopsys DFT Compiler, or Cadence Modus. - Proficiency in scripting languages such as TCL, Perl, or Python for design automation. - Knowledge of timing constraints, UPF, and low-power design and test methodologies. - Exposure to large ASIC applications in design or test.
Skills: SCAN, MBIST, BSCAN, ATPG, Tessent
This role has been open 89 days — well above the 59-day median for DFT Engineering roles.
DFT Engineering · DFT Test
|
Open roles in category
243
|
Median days open
59 d
|
Median salary
$203k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Intel Corporation | All employers we track in this specialty (243 roles · 53 employers) |
|---|---|---|
| Open roles in this specialty | 9 | 243 |
| Open roles in the wider Digital Design & Verification family | 84 | 3224 · 116 employers |
| Median days open | 71 d | 59 d (+12 d vs this employer) |
| Median salary (USD postings) | — | $203k |
Skills observed across this category: SCAN, MBIST, BSCAN, ATPG, Tessent
Who's hiring in this category
- AMD · 40 open roles · median 42 d
- NVIDIA · 23 open roles · median 37 d
- Qualcomm · 23 open roles · median 102 d
- NXP Semiconductors · 18 open roles · median 67 d
- Synopsys · 14 open roles · median 26 d
- Micron Technology · 10 open roles · median 66 d
How we counted: 243 open DFT Engineering (DFT Test) roles from 53 employers tracked in the SemiconductorJobs index, counted 19 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.