DFT Engineer - USA-TX-Austin - River Place B7, United States
$129,400 - $207,000 USD yearly
Originally posted 26 June 2026 by the employer.
About the role
As a member of the team, you will be responsible for various aspects of DFT, including MBIST and scan insertion, ATPG, ATE pattern development, and yield analysis.
What you'll do
- Participate in block and chip-level DFT implementation, developing and executing all related tasks. - Work on DFT lint checking, MBIST architecture, logic insertion, and scan insertion using industry-standard tools. - Perform ATPG and pattern simulation for both MBIST and scan. - Develop ATE patterns, manage the hand-off process, and perform silicon debugging. - Work closely with ATE engineers on yield improvement and analysis. - Collaborate with design, verification, and implementation teams during the DFT design phase, and with ATE and product development teams during silicon bring-up.
What you'll need
- Bachelor's in Engineering and 8+ years of related experience, or a Master's degree and 6+ years of related experience. - Experience in silicon bring-up and yield improvement. - Experience in RTL lint checking, scan compression, scan insertion, and the ATPG process. - Experience in MBIST architecture and insertion. - Experience analyzing and debugging simulation failures alongside digital logic fundamentals. - Knowledge of the Mentor Tessent or Synopsys DFT and simulation tool suites, with proficiency in Perl or other scripting languages.
Nice to have
- Experience in STA constraint development in DFT modes.
Skills: DFT, MBIST, scan insertion, ATPG, ATE pattern development
This role has been open 116 days — well above the 61-day median for DFT Engineering roles.
DFT Engineering · DFT Test
|
Open roles in category
248
|
Median days open
61 d
|
Median salary
$203k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Broadcom | All employers we track in this specialty (248 roles · 53 employers) |
|---|---|---|
| Open roles in this specialty | 7 | 248 |
| Open roles in the wider Digital Design & Verification family | 52 | 3283 · 116 employers |
| Median days open | 100 d | 61 d (+39 d vs this employer) |
| Median salary (USD postings) | — | $203k |
Skills observed across this category: DFT, MBIST, scan insertion, ATPG, ATE pattern development
Who's hiring in this category
- AMD · 39 open roles · median 43 d
- NVIDIA · 24 open roles · median 31 d
- Qualcomm · 23 open roles · median 105 d
- NXP Semiconductors · 19 open roles · median 45 d
- Synopsys · 15 open roles · median 28 d
- Intel Corporation · 10 open roles · median 62 d
How we counted: 248 open DFT Engineering (DFT Test) roles from 53 employers tracked in the SemiconductorJobs index, counted 22 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.