Verification, Validation & Test
Originally posted 14 August 2026 by the employer.
About the role
This role involves defining, designing, and verifying Design for Test (DFT) and Design for Debug (DFD) solutions for complex, high-performance SoCs.
What you'll do
- Collaborate with architects, hardware, and firmware engineers to understand new DFX features.
- Design and integrate DFX logic in complex SoCs.
- Build test plan documentation, accounting for interactions with other features, hardware, firmware, and software driver use cases.
- Estimate time required for new feature tests and changes to the test environment.
- Build directed and random verification tests.
- Debug test failures, identify root causes, and work with RTL and firmware engineers to resolve design defects and correct test issues.
- Review functional and code coverage metrics, modifying or adding tests to meet requirements.
What you'll need
- Bachelor’s or Master’s degree in Electrical Engineering, Computer Engineering, or a related field.
- Experience with DFT (Design for Test) and DFD (Design for Debug) architecture, design, and verification.
- Experience with JTAG, LBIST, MBIST, Scan, and ATPG.
- Familiarity with test pattern generation, bring-up, and debug on ATE.
- Experience with post-silicon bring-up.
- Experience with IP-level and ASIC verification.
- Experience debugging firmware and RTL code using simulation tools.
- Experience with Verilog, SystemVerilog, SystemC, and C++.
- Experience automating workflows in a distributed compute environment.
- Experience with UVM concepts and the SystemVerilog language.
- Experience with static timing analysis and constraints.
Nice to have
- Familiarity with the Tessent tools suite, including Scan and ATPG.
- Familiarity with ICL/PDL.
- Scripting language experience: Perl, Ruby, Makefile, and shell preferred.
Market context
This role has been open 64 days — slightly above the 57-day median for DFT Engineering roles.
DFT Engineering · DFT Test
|
Open roles in category
242
|
Median days open
57 d
|
Median salary
$203k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | AMD | All employers we track in this specialty (242 roles · 53 employers) |
|---|---|---|
| Open roles in this specialty | 39 | 242 |
| Open roles in the wider Digital Design & Verification family | 251 | 3202 · 115 employers |
| Median days open | 43 d | 57 d (−14 d vs this employer) |
| Median salary (USD postings) | — | $203k |
Who's hiring in this category
- AMD (this employer) · 39 open roles · median 43 d
- NVIDIA · 23 open roles · median 35 d
- Qualcomm · 23 open roles · median 100 d
- NXP Semiconductors · 18 open roles · median 65 d
- Synopsys · 14 open roles · median 24 d
- Micron Technology · 10 open roles · median 64 d
How we counted: 242 open DFT Engineering (DFT Test) roles from 53 employers tracked in the SemiconductorJobs index, counted 17 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.