DFT Engineer - New College Grad
$116,000 - $218,500 USD yearly
Originally posted 25 June 2026 by the employer. Relisted by the employer on 31 October 2026.
About the role
As a DFT Engineer at NVIDIA, you will work on end-to-end DFT architecture, verification, and post-silicon validation.
What you'll do
- Work on end-to-end DFT across methodology, deployment, and post-silicon lifecycle support.
- Partner with EDA tool vendors to develop capabilities supporting NVIDIA requirements, and collaborate with internal CAD on automations.
- Work with NVIDIA VLSI and Operations teams to deliver the scan feature across all product segments.
- Mentor junior engineers on test designs and trade-offs including cost and quality.
What you'll need
- Currently pursuing an MS or PhD (or equivalent experience).
- Knowledge in defining scan test plans, BIST including memories and IOs, fault modeling, ATPG, and fault simulation.
- Skills in verification and validation of test patterns and logic on multi-million gate designs using vendor tools.
- Exposure to multiple domains including RTL & clocks design, STA, place-n-route, and power to evaluate trade-offs.
- Experience in silicon debug and bring-up on the ATE with an understanding of pattern formats, failure processing, and test program development.
Nice to have
- Strong programming and scripting skills in Perl, Python, or Tcl.
Skills: scan test plans, BIST, fault modeling, ATPG, fault simulation, silicon debug
More semiconductor jobs: NVIDIA jobs · DFT engineer jobs · California jobs
This role has been open 171 days — well above the 58-day median for DFT Engineering roles.
DFT Engineering · DFT Test
|
Open roles in category
249
|
Median days open
58 d
|
Category median salary (all employers)
$206k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | NVIDIA | All employers we track in this specialty (249 roles · 54 employers) |
|---|---|---|
| Open roles in this specialty | 22 | 249 |
| Open roles in the wider Digital Design & Verification family | 256 | 3358 · 114 employers |
| Median days open | 53 d | 58 d (−5 d vs this employer) |
| Median salary (USD postings) | — | $206k |
Skills observed across this category: scan test plans, BIST, fault modeling, ATPG, fault simulation, silicon debug
Who's hiring in this category
- AMD · 36 open roles · median 52 d
- Qualcomm · 24 open roles · median 79 d
- NVIDIA (this employer) · 21 open roles · median 49 d
- NXP Semiconductors · 19 open roles · median 44 d
- Synopsys · 18 open roles · median 31 d
- Intel Corporation · 9 open roles · median 60 d
How we counted: 249 open DFT Engineering (DFT Test) roles from 54 employers tracked in the SemiconductorJobs index, counted 31 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.