DFT Engineer (Design for Testability) - Staff - Richardson, TX, United States
Originally posted 17 June 2026 by the employer.
Define and implement Design for Test architectures for High Bandwidth Memory (HBM) products.
About the role
As a Staff DFT Design Engineer, you will define, design, and integrate Design for Test (DFT) architectures for High Bandwidth Memory (HBM) products. This role ensures test coverage across wafer, die, stack, and system in package (SiP) test stages while balancing performance, power, area, and manufacturing cost.
What you'll do
- Define and implement HBM DFT architectures, including scan, MBIST, JTAG, boundary scan, TSV test, redundancy test, and at-speed test structures. - Develop DFT solutions for both base die and DRAM die, addressing stacked-die and cube-level test requirements. - Design and integrate test access mechanisms to support wafer probe, cube test, and SiP/system test flows. - Collaborate with Product Engineering and Test Enablement teams to align DFT features with manufacturing test flows and cost targets. - Support yield learning, failure analysis, silicon bring-up, and debug by enabling observability and controllability in silicon. - Work closely with logic, analog, layout, verification, and physical design teams to ensure DFT is correctly implemented and verified.
What you'll need
- Bachelor’s degree or Master’s degree (or equivalent experience) in Electrical Engineering, Computer Engineering, or a related field. - 5+ years DRAM or ASIC DFT Design or Verification experience. - Strong fundamentals in digital design and DFT concepts, including scan, MBIST, boundary scan, and JTAG. - Experience with RTL design using SystemVerilog or VHDL, along with logic integration. - Familiarity with semiconductor test flows from wafer probe through final test.
Nice to have
- Experience with HBM, DRAM, or advanced memory products. - Knowledge of TSV-based 3D integration and stacked-die test challenges. - Hands-on experience with at-speed test, compression, or advanced DFT methodologies. - Exposure to DFT security, customer-specific DFT interfaces, or custom test modes.
Skills: HBM DFT, scan, MBIST, JTAG, boundary scan, TSV test
This role has been open 189 days — well above the 62-day median for DFT Engineering roles.
DFT Engineering · DFT Test
|
Open roles in category
247
|
Median days open
62 d
|
Median salary
$206k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (247 roles · 55 employers) |
|---|---|---|
| Open roles in this specialty | 10 | 247 |
| Open roles in the wider Digital Design & Verification family | 106 | 3346 · 116 employers |
| Median days open | 74 d | 62 d (+12 d vs this employer) |
| Median salary (USD postings) | — | $206k |
Skills observed across this category: HBM DFT, scan, MBIST, JTAG, boundary scan, TSV test
Who's hiring in this category
- AMD · 36 open roles · median 48 d
- Qualcomm · 26 open roles · median 76 d
- NVIDIA · 21 open roles · median 45 d
- NXP Semiconductors · 19 open roles · median 50 d
- Synopsys · 16 open roles · median 30 d
- Intel Corporation · 10 open roles · median 55 d
How we counted: 247 open DFT Engineering (DFT Test) roles from 55 employers tracked in the SemiconductorJobs index, counted 27 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.