DFT Design Engineer - Austin, United States
Originally posted 31 July 2026 by the employer.
About the role
Cadence Design Systems is seeking an SoC/ASIC Digital Design Engineer focused on Design for Test (DFT) based in Austin, Texas.
What you'll do
- Execute DFT insertion flows, including basic scan chain insertion using synthesis or other software tools. - Implement compression scan insertion, LBIST, and other scan technologies. - Configure and integrate memory built-in self-test (MBIST). - Perform Automatic Test Pattern Generation (ATPG) using systematic quality metrics to achieve design test coverage goals. - Debug and analyze failures to improve fault coverage. - Verify ATPG testbenches and identify root causes of simulation mis-compares.
What you'll need
- 2 to 10 years of professional experience in SoC/ASIC Digital Design with a focus on Design for Test (DFT). - Hands-on experience with scan chain insertion, compression scan technologies, MBIST, and ATPG. - Working knowledge of JTAG 1149.1/6, IEEE 1500, and IEEE 1687 standards. - Hands-on knowledge of synthesis, verification, and debugging Verilog testbenches. - US citizenship.
Nice to have
- Knowledge of timing analysis and equivalency checks. - Prior experience with Cadence tools and flows.
Skills: Design for Test (DFT), scan chain insertion, MBIST, ATPG, JTAG
This role has been open 215 days — well above the 62-day median for DFT Engineering roles.
DFT Engineering · DFT Test
|
Open roles in category
247
|
Median days open
62 d
|
Median salary
$206k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Cadence Design Systems | All employers we track in this specialty (247 roles · 55 employers) |
|---|---|---|
| Open roles in this specialty | 6 | 247 |
| Open roles in the wider Digital Design & Verification family | 121 | 3346 · 116 employers |
| Median days open | 138 d | 62 d (+76 d vs this employer) |
| Median salary (USD postings) | — | $206k |
Skills observed across this category: Design for Test (DFT), scan chain insertion, MBIST, ATPG, JTAG
Who's hiring in this category
- AMD · 36 open roles · median 48 d
- Qualcomm · 26 open roles · median 76 d
- NVIDIA · 21 open roles · median 45 d
- NXP Semiconductors · 19 open roles · median 50 d
- Synopsys · 16 open roles · median 30 d
- Intel Corporation · 10 open roles · median 55 d
How we counted: 247 open DFT Engineering (DFT Test) roles from 55 employers tracked in the SemiconductorJobs index, counted 27 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.