Design Verification Tech Lead- SerDes/PHY IP - San Jose, California, United States
$160,000 - $200,000 USD yearly
Originally posted 21 September 2026 by the employer — open 0 days.
This role focuses on the functional verification of high-speed SerDes/PHY IP for rack-scale AI infrastructure.
About the role
This role involves owning the functional verification of high-speed SerDes/PHY IP, the connectivity engine powering rack-scale AI infrastructure. You will architect verification environments, drive coverage closure, and ensure first-pass silicon success for high-speed serial protocols including PCIe Gen 6/Gen 7, UALink, UCIe, and Ethernet.
What you'll do
- Architect UVM-based verification environments for SerDes/PHY IP, including PMA, PCS, and PHY-MAC interface layers.
- Define verification plans, coverage models, and sign-off criteria for high-speed serial link blocks.
- Drive methodology decisions across analog/mixed-signal co-simulation, gate-level simulation, and emulation flows.
- Develop SystemVerilog/UVM testbenches, sequences, scoreboards, and reference models for multi-Gbps SerDes lanes.
- Execute functional, performance, and corner-case verification across equalization, CDR, training, and link bring-up scenarios.
- Lead coverage analysis and closure, debug failures with designers, and drive regressions to clean tape-out.
What you'll need
- Bachelor's degree in Electrical Engineering, Computer Engineering, or related field.
- 8+ years of design verification experience on high-speed SerDes, PHY, or mixed-signal IP.
- Strong understanding of the physical layer, including equalization (CTLE, DFE, FFE), CDR, training sequences, and link bring-up.
- Expert-level proficiency in SystemVerilog and UVM.
- Hands-on experience with analog/mixed-signal co-simulation and Real Number Modeling (RNM).
- Working knowledge of one or more high-speed serial protocols: PCIe, UALink, UCIe, Ethernet, or CXL.
Nice to have
- MS or PhD in Electrical Engineering or Computer Engineering.
- Experience verifying PCIe Gen 6/Gen 7, UALink, or UCIe SerDes/PHY IP.
- Familiarity with emulation platforms (Palladium, Veloce, or ZeBu) and gate-level simulation flows.
- Scripting proficiency in Python or Perl for verification automation and regression management.
- Experience supporting post-silicon bring-up and correlating pre-silicon coverage with silicon results.
Skills: UVM, SystemVerilog, SerDes/PHY IP, high-speed serial protocols, PCIe Gen 6/7, Real Number Modeling
This role has been open 0 days — well below the 60-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1136
|
Median days open
60 d
|
Median salary
$188k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Astera Labs | All employers we track in this specialty (1136 roles · 94 employers) |
|---|---|---|
| Open roles in this specialty | 16 | 1136 |
| Open roles in the wider Digital Design & Verification family | 53 | 3032 · 114 employers |
| Median days open | 58 d | 60 d (−2 d vs this employer) |
| Median salary (USD postings) | — | $188k |
Skills observed across this category: UVM, SystemVerilog, SerDes/PHY IP, high-speed serial protocols, PCIe Gen 6/7, Real Number Modeling
Who's hiring in this category
- Qualcomm · 103 open roles · median 55 d
- AMD · 101 open roles · median 33 d
- NVIDIA · 89 open roles · median 67 d
- Synopsys · 58 open roles · median 22 d
- Micron Technology · 56 open roles · median 100 d
- SiFive · 52 open roles · median 48 d
How we counted: 1136 open Design Verification (Design Verification) roles from 94 employers tracked in the SemiconductorJobs index, counted 21 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.