Design Verification Tech Lead- SerDes/PHY IP - San Jose, California, United States

Originally posted 21 September 2026 by the employer — open 0 days.

This role focuses on the functional verification of SerDes/PHY IP, which powers rack-scale AI infrastructure.

About the role

This role involves owning the functional verification of high-speed SerDes/PHY IP. You will ensure first-pass silicon success on the analog/digital boundary that defines AI systems, specifically for multi-Gbps SerDes blocks that ship into advanced AI platforms including UALink, UCIe, PCIe Gen 6/Gen 7, and Ethernet-based connectivity products.

What you'll do

• Architect UVM-based verification environments for SerDes/PHY IP, including PMA, PCS, and PHY-MAC interface layers.
• Define verification plans, coverage models, and sign-off criteria for high-speed serial link blocks.
• Drive methodology decisions across analog/mixed-signal co-simulation, gate-level simulation, and emulation flows.
• Develop SystemVerilog/UVM testbenches, sequences, scoreboards, and reference models for multi-Gbps SerDes lanes.
• Execute functional, performance, and corner-case verification across equalization, CDR, training, and link bring-up scenarios.
• Lead coverage analysis, debug failures with designers, and drive regressions for tape-out.
• Verify PHY behavior against industry specifications including PCIe Gen 6/Gen 7, UALink, UCIe, and Ethernet PHY standards.
• Model and validate channel behavior, link training state machines, and analog handoff scenarios.
• Partner with analog/AMS designers on Real Number Modeling (RNM) and behavioral models for SerDes blocks.
• Mentor junior DV engineers and set technical direction across the verification team.
• Collaborate with SoC integration, firmware, post-silicon validation, and customer engineering teams.
• Contribute to verification IP reuse strategy and tooling improvements.

What you'll need

• Bachelor's degree in Electrical Engineering, Computer Engineering, or related field.
• 5+ years of design verification experience on high-speed SerDes, PHY, or mixed-signal IP.
• Strong understanding of the physical layer, including equalization (CTLE, DFE, FFE), CDR, training sequences, and link bring-up.
• Expert-level proficiency in SystemVerilog and UVM.
• Hands-on experience with analog/mixed-signal co-simulation and Real Number Modeling (RNM).
• Working knowledge of one or more high-speed serial protocols: PCIe, UALink, UCIe, Ethernet, or CXL.

Nice to have

• MS or PhD in Electrical Engineering or Computer Engineering.
• Experience verifying PCIe Gen 6/Gen 7, UALink, or UCIe SerDes/PHY IP.
• Familiarity with emulation platforms (Palladium, Veloce, or ZeBu) and gate-level simulation flows.
• Scripting proficiency in Python or Perl for verification automation and regression management.
• Experience supporting post-silicon bring-up and correlating pre-silicon coverage with silicon results.
• Ability to lead technically across a multi-disciplinary team.

Skills: UVM, SystemVerilog, SerDes/PHY IP, high-speed serial protocols, PCIe Gen 6/7, Real Number Modeling