Design Verification Intern, BS - Summer 2027 - United States
$30 - $59 USD yearly
Originally posted 5 September 2026 by the employer.
About the role
This role involves design verification to create powerful simulation environments and develop automated tests.
What you'll do
- Create simulation environments that mimic real-world conditions.
- Develop automated tests to find and troubleshoot hidden flaws and failed simulations.
- Analyze test coverage results and metrics.
- Collaborate with chip architects and designers to solve complex problems.
What you'll need
- Currently enrolled in a Bachelor’s Degree in Electrical Engineering, Computer Engineering, or a related field with an expected graduation date between Fall 2027 – Summer 2028.
- Completed courses focusing on computer architecture, logic, processor, memory system, Verilog, VLSI, VHDL, UVM, analog, integrated circuit design, digital logic design, SoC/ASIC design, verification principles, signals, system, and signal processing.
- Proficiency in programming and scripting languages like Python, C, C++, Perl, Java.
- Experience using tools like Synopsys, Cadence, or Mentor to run simulations and write and debug a testbench.
- Hands-on experience with RTL integration and bring-up system.
- Experience with debugging complex hardware/software interactions.
Skills: simulation environments, automated tests, UVM methodology, testbench, test coverage, SystemVerilog
This role has been open 24 days — well below the 63-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1169
|
Median days open
63 d
|
Median salary
$188k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Marvell Technology | All employers we track in this specialty (1169 roles · 95 employers) |
|---|---|---|
| Open roles in this specialty | 6 | 1169 |
| Open roles in the wider Digital Design & Verification family | 29 | 3113 · 115 employers |
| Median days open | 24 d | 63 d (−39 d vs this employer) |
| Median salary (USD postings) | — | $188k |
Skills observed across this category: simulation environments, automated tests, UVM methodology, testbench, test coverage, SystemVerilog
Who's hiring in this category
- AMD · 104 open roles · median 39 d
- Qualcomm · 97 open roles · median 53 d
- NVIDIA · 86 open roles · median 70 d
- Synopsys · 62 open roles · median 23 d
- SiFive · 57 open roles · median 56 d
- NXP Semiconductors · 52 open roles · median 76 d
How we counted: 1169 open Design Verification (Design Verification) roles from 95 employers tracked in the SemiconductorJobs index, counted 29 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.