Design Verification Engineer - Waltham, United States
Originally posted 28 August 2026 by the employer. Relisted by the employer on 27 October 2026.
About the role
This role is for a Design Verification Engineer responsible for enabling fully functional first silicon for IP designs and ensuring bug-free first silicon for part of the SoC / IP.
What you'll do
- Establish DV methodology and develop test plans.
- Develop verification environments, including stimulus, checkers, assertions, and trackers.
- Write tests, debug issues, and ensure coverage sign-off for RTL freeze and tape-out.
- Develop block, IP, and SoC level test-benches.
- Track and report DV progress using metrics, including bugs and coverage.
- Utilize LLM and related technologies for efficient execution and improved quality.
What you'll need
- BS degree in a technical subject area and a minimum 10 years relevant industry experience.
- Deep knowledge of OOP, SystemVerilog, and UVM.
- Experience with verification methodologies and tools such as simulators, waveform viewers, and build automation.
- Strong experience with coverage collection and gate level simulations.
- Excellent knowledge of one of the scripting languages such as Python, Perl, or TCL.
Nice to have
- Experience with power-aware (UPF) verification methodology.
- Working experience using LLMs for efficiency and quality.
- Experience with serial protocols such as PCIe or USB, or parallel protocols such as DDR.
- Knowledge of formal verification methodology.
- Knowledge of emulation for verification technologies.
Skills: pre-silicon verification, DV methodology, test-plan development, SystemVerilog, UVM, coverage
This role has been open 59 days — below the 67-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1268
|
Median days open
67 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Apple | All employers we track in this specialty (1268 roles · 96 employers) |
|---|---|---|
| Open roles in this specialty | 44 | 1268 |
| Open roles in the wider Digital Design & Verification family | 116 | 3328 · 116 employers |
| Median days open | 11 d | 67 d (−56 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: pre-silicon verification, DV methodology, test-plan development, SystemVerilog, UVM, coverage
Who's hiring in this category
- Qualcomm · 120 open roles · median 46 d
- NVIDIA · 93 open roles · median 66 d
- AMD · 92 open roles · median 56 d
- Synopsys · 67 open roles · median 42 d
- SiFive · 56 open roles · median 80 d
- Cadence Design Systems · 50 open roles · median 132 d
How we counted: 1268 open Design Verification (Design Verification) roles from 96 employers tracked in the SemiconductorJobs index, counted 27 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.