Design Verification Engineer - Memory Controller IP
$249,900 - $338,100 USD yearly
Verify Memory Controller IP using SystemVerilog and UVM across LPDDR and DDR technologies.
Originally posted 29 October 2026 by the employer.
About the role
As a Design Verification Engineer on the Memory Controller IP verification team, you will develop verification strategies and SystemVerilog/UVM environments to validate functionality, performance, and protocol behaviour. You will collaborate with RTL designers, architects, and verification colleagues to investigate issues, close verification on assigned features, and verify memory controller designs across supported LPDDR and DDR technologies.
What you'll do
- Develop and maintain SystemVerilog/UVM verification environments for Memory Controller IP.
- Create verification plans, test scenarios, assertions, functional coverage models, and scoreboards from architectural specifications.
- Develop constrained-random and directed tests to verify memory controller functionality across supported LPDDR and DDR technologies.
- Analyse regressions, coverage, simulation waveforms, and logs to identify and resolve RTL, testbench, and protocol issues.
- Partner with RTL designers, architects, and verification teams to clarify behaviour, resolve issues, and support verification sign-off.
- Improve verification efficiency through scripting, automation, and verification methodology improvements.
What you'll need
- Practical experience verifying ASIC or SoC designs using SystemVerilog and UVM, including constrained-random testing, assertions, scoreboards, and functional coverage.
- Ability to develop verification plans and translate architectural specifications into tests, coverage, and verification environments.
- Understanding of memory controller architecture and memory protocol concepts, including LPDDR or DDR technologies.
- Ability to debug RTL, testbench, and protocol issues using simulation tools, waveforms, and logs.
Nice to have
- Experience with LPDDR5, LPDDR6, DDR5, DDR6, or other memory technologies.
- Knowledge of DFI interfaces, including DFI 4.x or 5.x.
- Familiarity with AMBA protocols such as AXI, ACE, or CHI.
- Experience with simulation and debug tools such as Synopsys VCS or Siemens Questa.
- Experience improving verification workflows through scripting, automation, or methodology development.
Skills: SystemVerilog, UVM, Memory Controller IP, LPDDR, DDR
More semiconductor jobs: Verification engineer jobs · Austin jobs
This role has been open 0 days — well below the 58-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1293
|
Median days open
58 d
|
Category median salary (all employers)
$186k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Arm Holdings | All employers we track in this specialty (1293 roles · 98 employers) |
|---|---|---|
| Open roles in this specialty | 54 | 1293 |
| Open roles in the wider Digital Design & Verification family | 122 | 3314 · 115 employers |
| Median days open | 85 d | 58 d (+27 d vs this employer) |
| Median salary (USD postings) | — | $186k |
Skills observed across this category: SystemVerilog, UVM, Memory Controller IP, LPDDR, DDR
Who's hiring in this category
- Qualcomm · 113 open roles · median 42 d
- NVIDIA · 95 open roles · median 67 d
- AMD · 90 open roles · median 58 d
- Synopsys · 74 open roles · median 43 d
- Apple · 69 open roles · median 8 d
- SiFive · 56 open roles · median 82 d
How we counted: 1293 open Design Verification (Design Verification) roles from 98 employers tracked in the SemiconductorJobs index, counted 29 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.