Design Verification Engineer, Hardware - Palo Alto, CA
$200,000 - $420,000 USD yearly
Originally posted 15 May 2026 by the employer.
Verify custom silicon for local inference hardware using SystemVerilog, UVM, and emulation platforms.
About the role
As a Design Verification Engineer, Hardware, you will ensure high-performance custom silicon is functionally correct. Starting from architectural and micro-architectural definitions, you will define testbench boundaries and implement verification environments across simulation, formal, and emulation methodologies.
What you'll do
- Define comprehensive verification plans by extracting features from architectural and micro-architectural specifications for complex blocks. - Architect and implement scalable, reusable testbenches using SystemVerilog and UVM (Universal Verification Methodology). - Develop constrained-random sequences and test cases to achieve high functional coverage across corner cases and error conditions. - Define functional coverage models and analyze code coverage to quantify verification progress. - Leverage formal methods (SVA, Property Checking) to prove the correctness of critical logic. - Use emulation and prototyping platforms including ZeBu/HAPS and Palladium/Protium to perform scaled testing. - Debug failures with waveform viewers and collaborate with RTL designers to resolve bugs. - Build and maintain regression flows and productivity tools using Python, Perl, Bash, or TCL.
What you'll need
- Bachelor’s degree in Electrical Engineering, Computer Engineering, or Computer Science, and 5+ years of industry experience. - Hands-on experience building UVM-based environments (Agents, Scoreboards, Drivers, Monitors, and Predictors). - Command of SystemVerilog for verification, including OOP principles, randomization, and functional coverage. - Understanding of computer architecture, including pipelines, cache coherency protocols, memory consistency models, and high-speed interconnects (e.g., AXI, CHI). - Proven track record verifying high-performance silicon (CPU, GPU, AI accelerator, or complex SoC).
Nice to have
- Proficiency in SystemVerilog Assertions (SVA) and formal tools (Jasper, VC Formal). - Understanding of emulation and prototyping solutions and test environments. - Hands-on experience in post-silicon bringup, testing, and debug. - Experience with CI/CD, regression definition, and EDA tool configuration.
Skills: UVM, SystemVerilog, functional coverage, formal verification, emulation, AI accelerator
This role has been open 130 days — well above the 65-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1241
|
Median days open
65 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | River | All employers we track in this specialty (1241 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 1241 |
| Open roles in the wider Digital Design & Verification family | 3 | 3322 · 115 employers |
| Median days open | 77 d | 65 d (+12 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: UVM, SystemVerilog, functional coverage, formal verification, emulation, AI accelerator
Who's hiring in this category
- Qualcomm · 115 open roles · median 42 d
- AMD · 94 open roles · median 52 d
- NVIDIA · 85 open roles · median 64 d
- Synopsys · 66 open roles · median 38 d
- SiFive · 55 open roles · median 80 d
- Cadence Design Systems · 52 open roles · median 122 d
How we counted: 1241 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 23 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.