Design Verification Engineer (Einfochips) - San Jose, California (Cisco), United States
Originally posted 9 July 2026 by the employer. Relisted by the employer on 7 August 2026.
About the role
Arrow Electronics is seeking a Design Verification Engineer for eInfochips in San Jose, California to execute the complete verification cycle.
What you'll do
- Execute the complete verification cycle including test plan development, testbench component development, and coverage closure. - Develop and integrate BFM, Driver, Monitor, and Scoreboard components into SVTB and UVM environments. - Execute stress and corner testing, gate level simulations, failure debug, and assertion coding. - Build and maintain C++ and SVTB testbenches. - Interface with customers and report daily or weekly progress.
What you'll need
- At least 6+ years of experience in SystemVerilog HVL and C++/C. - At least 6+ years of experience in UVM. - Experience with scripting using Make, Perl, Python, or related languages. - Proven experience in failure debug, assertions coding, and gate level simulations.
Nice to have
- Understanding of DSP. - Experience with Subversion for repository management and Bugzilla.
Skills: SystemVerilog HVL, UVM, test plan development, test bench component, coverage closure, stress/corner testing
This role has been open 129 days — well above the 65-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1241
|
Median days open
65 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Arrow Electronics | All employers we track in this specialty (1241 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 5 | 1241 |
| Open roles in the wider Digital Design & Verification family | 11 | 3322 · 115 employers |
| Median days open | 129 d | 65 d (+64 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: SystemVerilog HVL, UVM, test plan development, test bench component, coverage closure, stress/corner testing
Who's hiring in this category
- Qualcomm · 115 open roles · median 42 d
- AMD · 94 open roles · median 52 d
- NVIDIA · 85 open roles · median 64 d
- Synopsys · 66 open roles · median 38 d
- SiFive · 55 open roles · median 80 d
- Cadence Design Systems · 52 open roles · median 122 d
How we counted: 1241 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 23 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.