Design Verification Engineer
Develop and execute verification methodologies and RTL simulation environments for proprietary DPU architectures.
About the role
This role involves verifying in-house accelerator IPs and performing comprehensive verification for complex systems encompassing commercial IPs and in-house IPs for IP, FPGA, and SoC developments. Engineers will construct verification environments, workflows, and methodologies for DPU solutions.
What you'll do
- Lead comprehensive system-level software/hardware verification and troubleshooting for MangoBoost DPUs using RTL simulation.
- Collaborate with cross-functional teams including IP Design, Software, Architecture, and SoC to validate the functionality and performance of DPU systems and applications.
- Evaluate system workflow and performance, providing recommendations for enhancements based on user feedback, complaints, and bug reports.
- Spearhead the development and implementation of HW-focused verification methodologies to enhance DPU product quality and efficiency.
What you'll need
- Bachelor's, Master's, or PhD in Electrical or Computer Engineering, Computer Science, or related field (Master's degree holders may apply as entry-level candidates).
- Experience in RTL simulation with Verilog or SystemVerilog.
- Experience in digital HW verification flow.
Nice to have
- 2+ years of industry experience in performance verification, measuring and analyzing DUT performance metrics.
- Ability to write UVM testbench code from scratch.
- Familiarity with protocols and standards in the AMBA, Ethernet, PCIe, and NVMe domains.
- Ability to establish comprehensive and concrete verification plans.
- Working experience in coverage-driven constrained random verification.
- Ability to model a system with the OOP (Object-Oriented Programming) paradigm.
- Strong background in computer architecture and operating systems.
- Experience in verifying ARM-based SoC scenarios with large-scale master/slave connections over NoC bus, including QoS behavior verification, using RTL simulation.
Skills: UVM, SystemVerilog, RTL simulation, DPU, coverage driven
More semiconductor jobs: Verification engineer jobs · South Korea jobs
First seen in our index 3 days ago, well below the 61-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1353
|
Median days since first seen
61 d
|
Category median salary (all employers)
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | MangoBoost | All employers we track in this specialty (1353 roles · 98 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 1353 |
| Open roles in the wider Digital Design & Verification family | 3 | 3499 · 119 employers |
| Median days since first seen | 3 d | 61 d (+58 d vs this employer) |
| Median salary (USD postings) | n/a | $185k |
Skills observed across this category: UVM, SystemVerilog, RTL simulation, DPU, coverage driven
Who's hiring in this category
- Qualcomm · 118 open roles · median 53 d
- Apple · 112 open roles · median 14 d
- NVIDIA · 105 open roles · median 75 d
- AMD · 84 open roles · median 71 d
- Synopsys · 74 open roles · median 55 d
- SiFive · 57 open roles · median 69 d
How we counted: 1353 open Design Verification (Design Verification) roles from 98 employers tracked in the SemiconductorJobs index, counted 11 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there, and is counted in the wider Digital Design & Verification family row. Days are counted from when our index first saw each posting, not from the employer's original posting date.