Design Verification Engineer - Austin Metro Area, United States
Originally posted 2 October 2026 by the employer.
About the role
This role is for a Design Verification Engineer to produce fully functional first silicon for IP designs.
What you'll do
- Establish DV methodology for IP designs.
- Develop detailed test and coverage plans based on micro-architecture.
- Develop scalable and portable verification environments, including stimulus, checkers, assertions, trackers, and coverage.
- Execute verification plans, including design bring-up, DV environment bring-up, and debug test failures.
- Track and report DV progress using metrics, including bugs and coverage.
- Utilize LLM and related technologies for efficient execution and improved quality.
What you'll need
- BS degree in technical discipline and a minimum 10 years relevant industry experience.
- Deep knowledge of OOP, SystemVerilog and UVM.
- Strong experience with verification methodologies and tools such as simulators, waveform viewers, build and run automation, and coverage collection.
- Excellent knowledge of one of the scripting languages such as Python, Perl, or TCL.
Nice to have
- Working experience using LLMs for efficiency and quality.
- Experience with power-aware (UPF) verification methodology.
- Experience with serial protocols such as PCIe or USB, or parallel protocols such as DDR.
- Knowledge of formal verification methodology.
- Knowledge of emulation for verification technologies.
Skills: SystemVerilog, UVM, test-plan development, test-writing, coverage, RTL freeze
This role has been open 12 days — well below the 65-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1192
|
Median days open
65 d
|
Median salary
$186k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Apple | All employers we track in this specialty (1192 roles · 95 employers) |
|---|---|---|
| Open roles in this specialty | 19 | 1192 |
| Open roles in the wider Digital Design & Verification family | 64 | 3189 · 115 employers |
| Median days open | 23 d | 65 d (−42 d vs this employer) |
| Median salary (USD postings) | — | $186k |
Skills observed across this category: SystemVerilog, UVM, test-plan development, test-writing, coverage, RTL freeze
Who's hiring in this category
- Qualcomm · 106 open roles · median 42 d
- AMD · 99 open roles · median 55 d
- NVIDIA · 82 open roles · median 57 d
- Synopsys · 63 open roles · median 30 d
- SiFive · 54 open roles · median 72 d
- Cadence Design Systems · 50 open roles · median 114 d
How we counted: 1192 open Design Verification (Design Verification) roles from 95 employers tracked in the SemiconductorJobs index, counted 15 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.