Verification of pre-silicon hardware IP including Neural Engine hardware, DRAM subsystems, hardware security, and high-speed IO standards.
About the role
This role involves creating software to verify the architecture and functionality of pre-silicon hardware designs in Austin, Texas. Verification scope spans SOC, subsystem, and IP blocks such as Neural Engine hardware, memory controllers, hardware security, codec engines, and high-speed IO interfaces.
What you'll do
- Develop test plans, testbenches, and coverage plans, defining verification methodology and test sequences.
- Simulate and debug Register Transfer Level (RTL) designs using waveform tools to triage regression failures.
- Program verification environments using object-oriented programming, C, C++, SystemVerilog, Python, and Perl.
- Run regressions, track bugs, and analyze both code coverage and functional coverage to close coverage holes.
- Review design and micro-architecture specifications in collaboration with design, architecture, and software teams.
- Write assertions to verify RTL for corner-case scenarios and drive complex use cases.
What you'll need
- Master's degree (or foreign equivalent) in Electrical Engineering, Computer Engineering, Electrical and Computer Engineering, or a related field plus 5 years of verification experience.
- Experience utilizing SystemVerilog and UVM to develop testbench code and test sequences for design blocks.
- Experience with NCSIM and Xcelium for waveform debug to investigate and triage regression failures.
- Experience using Python or Perl for scripting to create design verification collaterals.
- Experience writing assertions to verify RTL behavior across corner-case scenarios.
- Demonstrated understanding of computer architecture and digital design to evaluate micro-architecture and subsystem design blocks.
- Experience analyzing functional coverage and code coverage to find and resolve coverage holes in IP blocks.
Skills: SystemVerilog, UVM, Xcelium, RTL simulation, functional coverage, assertions
More semiconductor jobs: Apple jobs · Verification engineer jobs
This role has been open 0 days — well below the 57-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1317
|
Median days open
57 d
|
Category median salary (all employers)
$184k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Apple | All employers we track in this specialty (1317 roles · 99 employers) |
|---|---|---|
| Open roles in this specialty | 111 | 1317 |
| Open roles in the wider Digital Design & Verification family | 192 | 3500 · 120 employers |
| Median days open | 9 d | 57 d (−48 d vs this employer) |
| Median salary (USD postings) | — | $184k |
Skills observed across this category: SystemVerilog, UVM, Xcelium, RTL simulation, functional coverage, assertions
Who's hiring in this category
- Qualcomm · 117 open roles · median 49 d
- NVIDIA · 104 open roles · median 71 d
- Apple (this employer) · 99 open roles · median 9 d
- AMD · 83 open roles · median 65 d
- Synopsys · 73 open roles · median 50 d
- SiFive · 58 open roles · median 63 d
How we counted: 1317 open Design Verification (Design Verification) roles from 99 employers tracked in the SemiconductorJobs index, counted 5 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.