$121,900 - $195,000 USD yearly
Originally posted 11 November 2026 by the employer.
About the role
This role is responsible for leading and executing synthesis, static timing analysis (STA), formal verification, and low-power implementation activities for Mixed Signal (MXS) blocks. You will also serve as the IP Release Owner, managing critical integrity checks and release validation prior to IP block handoff.
What you'll do
- Execute synthesis and run static checks including CDC, RDC, and UPF/CPF power intent for digital and mixed-signal blocks.
- Create, validate, and maintain timing constraints, perform STA, and define timing signoff methodologies including corners and derating.
- Run formal verification and logical equivalence checking (LEC) throughout the design flow to guarantee functional correctness.
- Generate and implement timing and functional ECOs to drive timing closure, evaluating pre- and post-route Quality of Results (QoR).
- Drive the IP release validation flow, audit files for synchronization gaps, and ensure proper tagging via revision control utilities before handing off to customers or SoC teams.
- Build and deploy custom script-based automation using Tcl, Perl, or Python to streamline implementation and audit tasks.
What you'll need
- BS in Electrical Engineering, Computer Engineering, or a related field with 8+ years of related experience, or an MS with 6+ years of related experience.
- Experience with industry-standard tools for synthesis, STA, formal verification, and low-power audits, such as Design Compiler, Genus, PrimeTime, Tempus, Formality, or VCLP.
- Hands-on experience with hardware data management tools like Git or DesignSync for managing hierarchical IP releases.
- Strong familiarity with UPF/CPF low-power design methodologies.
- Automation skills developing custom tools using scripting languages including Tcl, Perl, or Python.
- Track record contributing to the successful tapeout or release deployment of at least 1–2 high-complexity ASICs/SoCs.
Nice to have
- Direct experience with physical design implementation steps including partitioning, floorplanning, placement, clock tree synthesis (CTS), routing, and physical verification (LVS/DRC using tools like Calibre, ICC2, or Innovus).
- Direct or indirect experience with RTL design and architecture.
Skills: synthesis, STA, formal verification, PrimeTime, UPF/CPF, timing closure
More semiconductor jobs: Broadcom jobs · Physical design jobs
First seen in our index 2 days ago, well below the 62-day median for Physical Design roles.
Physical Design · Physical Design
|
Open roles in category
753
|
Median days since first seen
62 d
|
Category median salary (all employers)
$187k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Broadcom | All employers we track in this specialty (753 roles · 90 employers) |
|---|---|---|
| Open roles in this specialty | 53 | 753 |
| Open roles in the wider Physical Implementation family | 58 | 1689 · 121 employers |
| Median days since first seen | 24 d | 62 d (+38 d vs this employer) |
| Median salary (USD postings) | n/a | $187k |
Skills observed across this category: synthesis, STA, formal verification, PrimeTime, UPF/CPF, timing closure
Who's hiring in this category
- Qualcomm · 119 open roles · median 66 d
- AMD · 66 open roles · median 45 d
- Broadcom (this employer) · 53 open roles · median 24 d
- NVIDIA · 46 open roles · median 85 d
- Synopsys · 44 open roles · median 43 d
- Apple · 32 open roles · median 8 d
How we counted: 753 open Physical Design (Physical Design) roles from 90 employers tracked in the SemiconductorJobs index, counted 14 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there, and is counted in the wider Physical Implementation family row. Days are counted from when our index first saw each posting, not from the employer's original posting date.