Design For Test Intern, MS - Summer 2027 - Santa Clara, CA, United States
Originally posted 17 September 2026 by the employer — open 0 days.
About the role
This intern role focuses on Design for Test (DFT) architecture solutions and methodology within Marvell's Compute and Custom Solutions (CCS) Business Unit, working on complex SoCs and processors in advanced process nodes.
What you'll do
- Develop understanding of block level or chip top DFT and pattern generation flows for complex SOC designs.
- Execute DFT insertion, pattern generation, and verification flows for Scan, Memory Built-in Self-Test (MBIST), Boundary Scan, and IP macro test.
- Run DFT checks and analyze results to resolve testability issues and improve DFT coverage.
- Support DFT flow automation through scripting (Tcl, Python, or shell).
- Contribute to DFT documentation, methodology improvements, and automation.
- Present intern project results to the team.
What you'll need
- Currently pursuing a Masters in Computer Engineering, Electrical Engineering, or related fields.
- Good understanding of digital logic design using Verilog/System Verilog.
- Knowledge of DFT concepts, JTAG standards, and Boundary scan implementation.
- Experience in programming and scripting languages such as Python, Shell, Tcl.
Nice to have
- Knowledge of Scan test, memory BIST/BISR, functional test, JTAG, and other test methodologies.
- Knowledge of using AI assisted tools for coding, scripts, and automation.
This role has been open 0 days — well below the 64-day median for DFT Engineering roles.
DFT Engineering · DFT Test
|
Open roles in category
211
|
Median days open
64 d
|
Median salary
$200k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Marvell Technology | All employers we track in this specialty (211 roles · 50 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 211 |
| Open roles in the wider Digital Design & Verification family | 23 | 3004 · 115 employers |
| Median days open | 6 d | 64 d (−58 d vs this employer) |
| Median salary (USD postings) | — | $200k |
Who's hiring in this category
- AMD · 35 open roles · median 43 d
- Qualcomm · 21 open roles · median 76 d
- NVIDIA · 19 open roles · median 65 d
- NXP Semiconductors · 16 open roles · median 74 d
- Micron Technology · 10 open roles · median 108 d
- Broadcom · 8 open roles · median 74 d
How we counted: 211 open DFT Engineering (DFT Test) roles from 50 employers tracked in the SemiconductorJobs index, counted 17 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.