Design For Test Enginineer IV - US-CA-San Jose, California, United States
Arrow Electronics
US-CA-San Jose, California, United States
1 month ago
Verification, Validation & Test
Originally posted 11 September 2026 by the employer.
About the role
This role involves ensuring successful delivery of Design For Test (DFT) deliverables from technical aspects. You will define and implement DFT solutions.
What you'll do
- Perform scan insertion, JTAG, ATPG DRC, and coverage analysis.
- Debug and find root cause of simulation failures, including those with timing/SDF.
- Work with design teams to define and implement DFT solutions.
- Enhance DFT best practices through new methodology, technology, and tools.
- Collaborate with clients and technical teams to execute concurrent objectives.
- Envision and tailor new technology usage for desired results.
What you'll need
- Minimum of 8 years of related experience with a 4-year degree; or 6 years with an advanced degree; or equivalent experience.
- In-depth knowledge and experience in DFT.
- Ability to solve complex problems and work independently.
- Strong analytical skills and capability to analyze business practices.
Nice to have
- Experience leading the work of project teams.
- Experience formally training junior staff.
Market context
This role has been open 33 days — well below the 56-day median for DFT Engineering roles.
DFT Engineering · DFT Test
|
Open roles in category
250
|
Median days open
56 d
|
Median salary
$205k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Arrow Electronics | All employers we track in this specialty (250 roles · 53 employers) |
|---|---|---|
| Open roles in this specialty | 3 | 250 |
| Open roles in the wider Digital Design & Verification family | 10 | 3191 · 115 employers |
| Median days open | 34 d | 56 d (−22 d vs this employer) |
| Median salary (USD postings) | — | $205k |
Who's hiring in this category
- AMD · 40 open roles · median 41 d
- NVIDIA · 25 open roles · median 41 d
- Qualcomm · 24 open roles · median 101 d
- NXP Semiconductors · 18 open roles · median 63 d
- Synopsys · 13 open roles · median 23 d
- Micron Technology · 11 open roles · median 54 d
How we counted: 250 open DFT Engineering (DFT Test) roles from 53 employers tracked in the SemiconductorJobs index, counted 15 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.
Arrow Electronics
US-CA-San Jose, California, United States
On-site
1 month ago