Design For Test Engineer IV (IC) - US-CA-San Jose, California, United States
Originally posted 13 April 2026 by the employer.
Deliver DFT implementation and pattern verification for 3nm and 5nm networking chips using Mentor Tessent, Cadence Modus, and Synopsys TetraMAX.
About the role
This role executes DFT implementation and verification for 3nm and 5nm networking chips and IP blocks.
What you'll do
- Perform DFT implementation and IP DFT work for 3nm and 5nm networking chips. - Run RTL checks for scan-insertion compatibility using Synopsys SpyGlass and execute scan-insertion using Tessent TestKompress. - Generate compressed and uncompressed ATPG patterns using Mentor Tessent, Cadence Modus, and Synopsys TetraMAX. - Run pattern simulations with and without timing across corners using VCS, and debug mismatches using Verdi. - Perform MBIST insertion and verification at block and top levels, including IEEE 1149.1 JTAG insertion and verification. - Support block and top silicon debug and bring-up, and automate flows using Perl, Shell, and TCL scripting.
What you'll need
- 5–7 years of experience in DFT. - Hands-on experience with scan-insertion, ATPG, GLS, and pattern simulations (with and without timing). - Proven experience with MBIST insertion and verification and IEEE 1149.1 JTAG insertion and verification. - Experience with multi-million gate count SoCs in networking, consumer, and IPs such as PLL and SerDes. - Proficiency in tools including Mentor Tessent and scripting in Perl, Shell, or TCL. - Experience with low power DFT. - B.Tech or M.Tech in Microelectronics or Electronics.
This role has been open 129 days — well above the 63-day median for DFT Engineering roles.
DFT Engineering · DFT Test
|
Open roles in category
248
|
Median days open
63 d
|
Median salary
$205k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Arrow Electronics | All employers we track in this specialty (248 roles · 53 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 248 |
| Open roles in the wider Digital Design & Verification family | 11 | 3322 · 115 employers |
| Median days open | 86 d | 63 d (+23 d vs this employer) |
| Median salary (USD postings) | — | $205k |
Who's hiring in this category
- AMD · 39 open roles · median 44 d
- Qualcomm · 25 open roles · median 77 d
- NVIDIA · 23 open roles · median 41 d
- NXP Semiconductors · 19 open roles · median 46 d
- Synopsys · 15 open roles · median 29 d
- Intel Corporation · 10 open roles · median 63 d
How we counted: 248 open DFT Engineering (DFT Test) roles from 53 employers tracked in the SemiconductorJobs index, counted 23 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.