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Cadence Design Systems

Design Engineer II - Austin, United States

Cadence Design Systems AUSTIN, United States 16 days ago
Verification, Validation & Test

Originally posted 25 September 2026 by the employer.

About the role

This role focuses on developing and enhancing the functional verification environment for Cadence's Memory Controller IP.

What you'll do

  • Add new features to the existing functional verification environment.
  • Ensure customer configurations are clean as part of verification regressions.
  • Support customers with issues related to the verification environment.
  • Perform functional and code coverage analysis.
  • Ensure design adheres to technical and quality requirements.

What you'll need

  • BS/MS in Electrical or Computer Engineering.
  • 2-3 years of relevant design verification experience.
  • Strong background in functional verification fundamentals, environment planning, test plan generation, and environment development.
  • Experience with UVM based functional verification environment development.

Skills: functional verification, UVM, test plan generation, memory controller, AXI

Market context

This role has been open 15 days — well below the 64-day median for Design Verification roles.

Design Verification · Design Verification

Open roles in category
1189
Median days open
64 d
Median salary
$187k
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
How Cadence Design Systems compares in Design Verification hiring
Metric Cadence Design Systems All employers we track in this specialty (1189 roles · 95 employers)
Open roles in this specialty 51 1189
Open roles in the wider Digital Design & Verification family 123 3166 · 114 employers
Median days open 109 d 64 d (+45 d vs this employer)
Median salary (USD postings) — $187k

Skills observed across this category: functional verification, UVM, test plan generation, memory controller, AXI

Who's hiring in this category

  • Qualcomm · 106 open roles · median 43 d
  • AMD · 103 open roles · median 50 d
  • NVIDIA · 74 open roles · median 64 d
  • Synopsys · 61 open roles · median 26 d
  • SiFive · 54 open roles · median 67 d
  • Cadence Design Systems (this employer) · 51 open roles · median 109 d

How we counted: 1189 open Design Verification (Design Verification) roles from 95 employers tracked in the SemiconductorJobs index, counted 10 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.

Apply now
AUSTIN, United States
On-site
16 days ago

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