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Synopsys

DDR/LPDDR IP Design Staff Engineer

Synopsys img src="https://tbcdn.talentbrew.com/company/44408/gst_v1/img/icon-map-black.png" height="15" width="15" alt="pin icon">Wuhan, China 13 days ago
Digital Design & SoC Architecture

Originally posted 22 September 2026 by the employer.

This role focuses on DDR/LPDDR IP design.

About the role

This role is for a Staff Engineer focused on DDR/LPDDR IP design and verification. You will contribute to high-end designs and support DDR/LPDDR products.

What you'll do

  • Work on digital design based on predefined RTL coding style.
  • Clean RTL check violations in lint, CDC, DFT, and synthesis.
  • Debug simulation and silicon issues.
  • Interact with different design groups and customer support teams.

What you'll need

  • BSEE with 6+ years of digital design experience or MSEE with 3+ years of relevant experience.
  • Experience with Verilog and System Verilog.
  • Solid debugging skills and ability to root cause issues.
  • Knowledge of SNPS EDA tools like VCS, Verdi, Spyglass, DC, Formality.
  • Good communication skills.

Nice to have

  • Knowledge in interface technologies such as DDR, HBM, UCIe.
  • Scripting experience in Shell, Perl, Python, and TCL.
  • Knowledge of analogic circuit.

Skills: DDR, LPDDR, RTL, Verilog, SystemVerilog

Market context

This role has been open 0 days — well below the 63-day median for Digital/RTL Design roles.

Digital/RTL Design · RTL Design

Open roles in category
972
Median days open
63 d
Median salary
$184k
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
How Synopsys compares in Digital/RTL Design hiring
Metric Synopsys All employers we track in this specialty (972 roles · 101 employers)
Open roles in this specialty 60 972
Open roles in the wider Digital Design & Verification family 137 3097 · 114 employers
Median days open 20 d 63 d (−43 d vs this employer)
Median salary (USD postings) — $184k

Skills observed across this category: DDR, LPDDR, RTL, Verilog, SystemVerilog

Who's hiring in this category

  • Qualcomm · 147 open roles · median 48 d
  • AMD · 66 open roles · median 65 d
  • Synopsys (this employer) · 59 open roles · median 20 d
  • NXP Semiconductors · 53 open roles · median 70 d
  • Analog Devices · 49 open roles · median 54 d
  • NVIDIA · 48 open roles · median 48 d

How we counted: 972 open Digital/RTL Design (RTL Design) roles from 101 employers tracked in the SemiconductorJobs index, counted 24 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.

Synopsys

Synopsys

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img src="https://tbcdn.talentbrew.com/company/44408/gst_v1/img/icon-map-black.png" height="15" width="15" alt="pin icon">Wuhan, China
On-site
13 days ago

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