Custom HBM Architecture and Design Engineer - United States
$165,000 - $329,000 USD yearly
Originally posted 22 June 2026 by the employer. Relisted by the employer on 3 September 2026.
About the role
As a Custom HBM Architecture and Design Engineer, you will contribute to the architecture, design, development, and integration of HBM SoC logic die. This role focuses on the Heterogeneous Integration Group (HIG) and HBM-based hardware.
What you'll do
- Analyze hardware and software interaction at the system level to identify bottlenecks in existing AI/ML workloads and HBM-based hardware.
- Drive future HBM architecture, design, and technology to address bottlenecks, including implementing proof of concept designs.
- Architect, design, and implement RTL for SoC-level blocks and subsystems used in HBM logic die.
- Architect and design memory sub-systems including memory IP selection and integration, bus and protocol selection, and power/performance/area optimization.
- Integrate internal and third-party IP (e.g., controllers, microcontrollers, NOC, RAS, MBIST, interfaces, adapters, buffers, PHY-adjacent logic).
- Assist with pre-silicon validation and post-silicon bring-up, including root-cause analysis of silicon issues.
What you'll need
- Bachelor’s or master’s degree in electrical engineering, computer engineering, or a related field, with a minimum of 10 years of experience.
- Proficiency in SystemVerilog/Verilog and familiarity with SoC integration methodologies.
- Experience with the RTL-to-GDS flow, including synthesis, static timing analysis, and sign-off considerations.
- Familiarity with EDA tools from Cadence, Synopsys, and/or Siemens.
- Programming or scripting experience (e.g., Python, TCL, Perl, or shell scripting).
Nice to have
- Experience with HBM, DRAM, or memory-centric SoC designs.
- Familiarity with high-speed interfaces, clocking strategies, reset architectures, and power management concepts.
- Exposure to DFT concepts (scan, MBIST, BIRA/BISR) and debug.
- Experience with hardware emulation or acceleration platforms (e.g., Palladium, Veloce, Zebu).
Skills: HBM architecture, memory sub-systems, RTL for SoC, RTL-to-GDS flow, pre-silicon validation
This role has been open 104 days — well above the 69-day median for Memory Design roles.
Memory Design · Memory Design
|
Open roles in category
287
|
Median days open
69 d
|
Median salary
$205k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Micron Technology | All employers we track in this specialty (287 roles · 29 employers) |
|---|---|---|
| Open roles in this specialty | 153 | 287 |
| Median days open | 86 d | 69 d (+17 d vs this employer) |
| Median salary (USD postings) | — | $205k |
Skills observed across this category: HBM architecture, memory sub-systems, RTL for SoC, RTL-to-GDS flow, pre-silicon validation
Who's hiring in this category
- Micron Technology (this employer) · 151 open roles · median 86 d
- Synopsys · 27 open roles · median 49 d
- SanDisk · 17 open roles · median 32 d
- Broadcom · 16 open roles · median 50 d
- Qualcomm · 12 open roles · median 149 d
- NVIDIA · 7 open roles · median 59 d
How we counted: 287 open Memory Design (Memory Design) roles from 29 employers tracked in the SemiconductorJobs index, counted 5 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.