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Qualcomm

CPU SRAM Design & Layout Engineer

Qualcomm Santa Clara, California, United States of America, United States 26 days ago
Digital Design & SoC Architecture

$147,900 - $221,900 USD yearly

Originally posted 9 September 2026 by the employer.

This role involves the design, analysis, implementation, and physical realization of high-performance custom SRAMs and register files.

About the role

This role involves the design, analysis, implementation, and physical realization of high-performance custom SRAMs and register files. You will own memory development from schematic capture and circuit design through layout implementation, verification, characterization, and model generation.

What you'll do

  • Design and develop custom SRAM and register file circuits optimized for high performance, low power, and scalability.
  • Create schematics and perform circuit-level design and optimization.
  • Develop memory floorplans and custom layouts based on project requirements and schematics.
  • Perform and oversee layout construction, verification, and optimization.
  • Execute and analyze LVS, DRC, ERC, and other physical verification checks.
  • Generate and validate all required memory deliverables and collateral models.

What you'll need

  • Bachelor's degree in Electrical Engineering or related field with 5 years of relevant industry experience OR Master's degree in Electrical Engineering with 2 years of relevant industry experience.
  • Experience designing custom SRAM circuits and register files.
  • Experience with custom memory layout design and implementation.
  • Experience using industry-standard custom design tools and methodologies.
  • Experience with circuit simulation, Monte Carlo analysis, and static timing analysis.
  • Knowledge of advanced semiconductor technologies, including FinFET and nanosheet process nodes.
  • Experience with deep sub-micron layout design for memory, datapath, and standard cell circuits.
  • Knowledge of layout floorplanning, hierarchical assembly, and physical verification methodologies.
  • Experience with Cadence Virtuoso and Calibre LVS/DRC verification flows.

Nice to have

  • Strong understanding of SRAM and register file architectures with advanced custom circuit implementations.
  • Strong understanding of high-performance and low-power circuit design techniques.
  • Strong knowledge of semiconductor device physics and reliability considerations.
  • Experience with variation-aware simulation methodologies in advanced technology nodes.
  • Experience with complete memory development flows, including: Design entry, Functional verification, Layout implementation and guidance, Simulation and characterization, Timing and power analysis, Electrical characterization, Deliverable model generation.
  • Experience with memory logical models (Verilog) and functional verification.
  • Experience with BIST and DFT methodologies.
  • Experience developing memory analysis flows and automation methodologies.
  • Knowledge of EMIR analysis and mitigation techniques.
  • Proficiency with tools such as NanoTime, Ansys EMIR, ESP-CV, and Liberate.
  • Experience writing SKILL code or other automation scripts for layout and design productivity.

Skills: custom SRAMs, register files, schematic capture, layout implementation, physical verification

Market context

This role has been open 25 days — well below the 69-day median for Memory Design roles.

Memory Design · Memory Design

Open roles in category
287
Median days open
69 d
Median salary
$205k
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
How Qualcomm compares in Memory Design hiring
Metric Qualcomm All employers we track in this specialty (287 roles · 29 employers)
Open roles in this specialty 12 287
Median days open 150 d 69 d (+81 d vs this employer)
Median salary (USD postings) — $205k

Skills observed across this category: custom SRAMs, register files, schematic capture, layout implementation, physical verification

Who's hiring in this category

  • Micron Technology · 151 open roles · median 86 d
  • Synopsys · 27 open roles · median 49 d
  • SanDisk · 17 open roles · median 32 d
  • Broadcom · 16 open roles · median 50 d
  • Qualcomm (this employer) · 12 open roles · median 149 d
  • NVIDIA · 7 open roles · median 59 d

How we counted: 287 open Memory Design (Memory Design) roles from 29 employers tracked in the SemiconductorJobs index, counted 5 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.

Apply now
Santa Clara, California, United States of America, United States
On-site
$147,900 - $221,900 USD yearly
26 days ago

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