CPU IP Design & Verification Intern – RISC-V Processor Development (Summer 2027)
$20 - $40 USD hourly
Originally posted 23 October 2026 by the employer.
Join the MIPS CPU IP Engineering organization to design and verify RISC-V processor IP.
About the role
Join the MIPS CPU IP Engineering organization for hands-on experience in the design and verification of RISC-V processor IP. You will collaborate with CPU architects, RTL designers, and verification engineers on CPU microarchitecture, RTL implementation, functional verification, and debug.
What you'll do
- Support RISC-V CPU microarchitecture and SystemVerilog RTL design and development. - Contribute to CPU functions including instruction fetch and decode, execution, load/store, caches and memory interfaces, control and status registers, exceptions, and interrupts. - Develop verification tests, assertions, checkers, and functional coverage for CPU features. - Run CPU simulations and regressions, debugging failures using logs, architectural traces, and waveforms. - Support CPU power, performance, and area analysis and optimization. - Develop Python, C/C++, or scripting-based automation to improve design, verification, regression, and debug productivity.
What you'll need
- Currently enrolled as at least a sophomore pursuing a Bachelor's, Master's, or PhD in Electrical Engineering, Computer Engineering, or related field with at least a 3.0 GPA. - Coursework or project experience in digital logic design and computer architecture. - Familiarity with Verilog or SystemVerilog. - Understanding of CPU fundamentals including pipelines, instruction execution, loads/stores, caches, and memory hierarchy. - Programming or scripting experience with Python, C/C++, or similar languages. - Availability to work at least 40 hours per week during the internship.
Nice to have
- Knowledge of the RISC-V Instruction Set Architecture (ISA). - Experience with SystemVerilog/UVM, assertions, functional coverage, or constrained-random verification. - CPU architecture, microarchitecture, FPGA, ASIC, or processor-design project experience. - Familiarity with caches, memory subsystems, privilege modes, exceptions, interrupts, or virtual memory. - Experience with simulation, waveform debug, Git, and Linux. - Exposure to synthesis, lint, clock-domain crossing analysis, formal verification, or timing analysis. - Assembly-language programming experience.
Skills: RISC-V, SystemVerilog, RTL, microarchitecture, verification
This role has been open 0 days — well below the 63-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1078
|
Median days open
63 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | GlobalFoundries | All employers we track in this specialty (1078 roles · 103 employers) |
|---|---|---|
| Open roles in this specialty | 17 | 1078 |
| Open roles in the wider Digital Design & Verification family | 46 | 3322 · 115 employers |
| Median days open | 38 d | 63 d (−25 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: RISC-V, SystemVerilog, RTL, microarchitecture, verification
Who's hiring in this category
- Qualcomm · 157 open roles · median 59 d
- Synopsys · 88 open roles · median 36 d
- AMD · 76 open roles · median 41 d
- Analog Devices · 49 open roles · median 52 d
- NXP Semiconductors · 42 open roles · median 91 d
- NVIDIA · 40 open roles · median 63 d
How we counted: 1078 open Digital/RTL Design (RTL Design) roles from 103 employers tracked in the SemiconductorJobs index, counted 23 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.