CPU IP Design & Verification Engineer – RISC-V (2027 New College Graduate) - Austin, Texas, United States of America
$86,000 - $170,000 USD yearly
Originally posted 23 October 2026 by the employer.
Develop and verify RISC-V processor IP on the MIPS CPU IP Engineering team.
About the role
GlobalFoundries is seeking a New College Graduate CPU IP Design & Verification Engineer to join the MIPS CPU IP Engineering team to develop and verify RISC-V processor IP. The position focuses on CPU microarchitecture, SystemVerilog RTL implementation, functional verification, and power, performance, and area analysis.
What you'll do
- Design and develop RISC-V CPU microarchitecture and SystemVerilog RTL. - Implement CPU functions including instruction fetch and decode, execution, load/store, caches, memory interfaces, control and status registers, exceptions, and interrupts. - Develop verification tests, assertions, checkers, and functional coverage for CPU features. - Run CPU simulations and regressions, debugging failures using logs, architectural traces, and waveforms. - Support functional and coverage closure through design and verification reviews. - Develop Python, C/C++, or scripting-based automation to improve design, verification, regression, and debug productivity.
What you'll need
- Graduating with a Bachelor’s, Master’s, or PhD in Electrical Engineering, Computer Engineering, or related field with at least an overall 3.0 GPA. - Foundation in digital logic design and computer architecture. - Coursework, research, internship, or project experience with Verilog or SystemVerilog. - Understanding of CPU fundamentals including pipelines, instruction execution, loads/stores, caches, and memory hierarchy. - Programming or scripting experience with Python, C/C++, or similar languages. - English language fluency (written and verbal).
Nice to have
- Prior related internship or co-op experience. - Knowledge of the RISC-V Instruction Set Architecture (ISA). - Experience with SystemVerilog/UVM, assertions, functional coverage, or constrained-random verification. - CPU architecture, microarchitecture, FPGA, ASIC, or processor-design project experience. - Familiarity with caches, memory subsystems, privilege modes, exceptions, interrupts, or virtual memory. - Experience with simulation, waveform debug, Git, and Linux. - Exposure to synthesis, lint, clock-domain crossing analysis, formal verification, or timing analysis. - Assembly-language programming experience.
Skills: RISC-V, SystemVerilog, RTL, CPU microarchitecture, simulation
This role has been open 0 days — well below the 63-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1078
|
Median days open
63 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | GlobalFoundries | All employers we track in this specialty (1078 roles · 103 employers) |
|---|---|---|
| Open roles in this specialty | 17 | 1078 |
| Open roles in the wider Digital Design & Verification family | 46 | 3322 · 115 employers |
| Median days open | 38 d | 63 d (−25 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: RISC-V, SystemVerilog, RTL, CPU microarchitecture, simulation
Who's hiring in this category
- Qualcomm · 157 open roles · median 59 d
- Synopsys · 88 open roles · median 36 d
- AMD · 76 open roles · median 41 d
- Analog Devices · 49 open roles · median 52 d
- NXP Semiconductors · 42 open roles · median 91 d
- NVIDIA · 40 open roles · median 63 d
How we counted: 1078 open Digital/RTL Design (RTL Design) roles from 103 employers tracked in the SemiconductorJobs index, counted 23 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.