Chief Engineer & Architect, MRAM - San Jose, United States
Originally posted 23 October 2026 by the employer.
About the role
This role serves as the most senior technical individual contributor in memory design, owning end-to-end product architecture from concept through silicon qualification. The position arbitrates power, performance, and area trade-offs while serving as the technical authority across design, process, and product engineering.
What you'll do
- Define the memory subsystem architecture, including array, periphery, I/O, redundancy, test, and reliability, translating product requirements into design specifications. - Drive floorplan and physical architecture, addressing array efficiency, periphery partitioning, power delivery, and die-level signal integrity. - Own multi-generation technology roadmaps for node migration, density, and performance scaling. - Decide cross-functional trade-offs across process integration, circuits, DFT, packaging, and controller or firmware interfaces. - Own the design methodology and EDA/CAD strategy across tools, flows, vendors, and licenses. - Mentor senior and principal engineers through architecture and design reviews while representing the architecture to executives, customers, foundry partners, and standards bodies.
What you'll need
- MS or PhD in Electrical Engineering, Computer Engineering, or a related field. - 15+ years of experience in memory or mixed-signal IC development, including 5+ years as an architect or chief engineer. - Track record of owning 2+ memory products from architecture through production silicon. - Deep advanced CMOS FinFET expertise covering layout, variability, reliability, and DFM. - Broad memory architecture knowledge spanning DRAM, NAND/NOR, SRAM, and emerging NVM, with depth in one domain. - Hands-on experience with modern Cadence and Synopsys custom and digital flows through full-chip sign-off. - Experience directing EDA/CAD strategy and leading multi-site programs through influence.
Nice to have
- Experience with embedded memory IP integration into SoCs and memory-controller co-design. - Direct foundry engagement on PDKs, test chips, and DTCO. - Expertise in emerging NVM architecture, active participation in JEDEC, or relevant patents and publications.
Skills: MRAM, memory architecture, emerging NVM, FinFET, die floorplan
This role has been open 0 days — well below the 67-day median for Memory Design roles.
Memory Design · Memory Design
|
Open roles in category
308
|
Median days open
67 d
|
Median salary
$200k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Western Digital | All employers we track in this specialty (308 roles · 30 employers) |
|---|---|---|
| Open roles in this specialty | 1 | 308 |
| Median days open | 0 d | 67 d (−67 d vs this employer) |
| Median salary (USD postings) | — | $200k |
Skills observed across this category: MRAM, memory architecture, emerging NVM, FinFET, die floorplan
Who's hiring in this category
- Micron Technology · 157 open roles · median 87 d
- Synopsys · 31 open roles · median 63 d
- Qualcomm · 19 open roles · median 84 d
- SanDisk · 17 open roles · median 50 d
- Broadcom · 16 open roles · median 64 d
- NVIDIA · 8 open roles · median 45 d
How we counted: 308 open Memory Design (Memory Design) roles from 30 employers tracked in the SemiconductorJobs index, counted 23 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there. Figures refresh nightly.