Originally posted 11 September 2026 by the employer.
This role focuses on predicting, validating, and explaining competitive server CPU performance for x86, Arm, and cloud-custom platforms.
About the role
This role involves establishing the Advanced Competitive Performance capability, setting the standard for predicting, validating, and communicating future server CPU competitiveness across x86, Arm, cloud-custom, and CPU-plus-accelerator platforms.
What you'll do
- Set the technical strategy, workload priorities, and operating rhythm for AMD competitive CPU performance forecasting.
- Own the predict-validate-translate cycle: workload taxonomy, architecture and platform assumptions, forecast ranges, validation, model tuning, and business translation.
- Lead reviews of assumptions covering CPU cores, cache and memory hierarchies, I/O, power, platform behavior, software stacks, and workload scaling.
- Establish a review discipline that distinguishes measured results, sourced assumptions, modeled inference, and uncertainty.
- Integrate x86, Arm, cloud-custom, and CPU-plus-accelerator analyses into one decision-ready view of competitive risks and expected AMD advantage.
- Deliver concise executive readouts that explain expected position, confidence, key drivers, and recommended actions.
What you'll need
- Demonstrated senior technical leadership in CPU or system performance, computer architecture, performance modeling, or competitive benchmarking.
- A record of turning low-level performance evidence into architecture, platform, or product decisions.
- Deep understanding of CPU pipelines, branch prediction, execution resources, cache and TLB behavior, NUMA, memory bandwidth and latency, system I/O, and cross-ISA effects.
- Strong command of experimental design, benchmark fairness, configuration control, statistical interpretation, and reproducibility.
- Exceptional written and verbal communication, including the ability to present risk, confidence, alternatives, and recommended action to senior audiences.
- Experience working across architecture, software, platform, product, field or customer, and business stakeholders.
Nice to have
- Direct experience with AMD EPYC, Intel Xeon, Arm Neoverse, or cloud-custom server CPUs.
- Pre-silicon performance modeling, architectural simulators, silicon performance counters, or platform telemetry.
- Partner, customer, or OEM performance-lab collaboration and cross-company benchmark validation.
- AI host-CPU or system analysis, accelerator utilization, rack power, density, or system-level TCO.
- Define a new technical capability and its standards rather than inherit a mature process.
- Influence decisions across CPU architecture, software, platform engineering, product planning, and executive leadership.
- Make long-range competitive forecasts technically honest, measurable, and operationally useful.
This role has been open 33 days — well below the 61-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1021
|
Median days open
61 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | AMD | All employers we track in this specialty (1021 roles · 103 employers) |
|---|---|---|
| Open roles in this specialty | 70 | 1021 |
| Open roles in the wider Digital Design & Verification family | 255 | 3191 · 115 employers |
| Median days open | 36 d | 61 d (−25 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Who's hiring in this category
- Qualcomm · 134 open roles · median 64 d
- Synopsys · 86 open roles · median 29 d
- AMD (this employer) · 72 open roles · median 35 d
- Analog Devices · 49 open roles · median 47 d
- NVIDIA · 46 open roles · median 63 d
- NXP Semiconductors · 41 open roles · median 84 d
How we counted: 1021 open Digital/RTL Design (RTL Design) roles from 103 employers tracked in the SemiconductorJobs index, counted 15 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.