Skip to main content
Intel Corporation

Back-End TD Reliability Lab Manager - Arizona, Phoenix, United States

Intel Corporation US, Arizona, Phoenix, United States 2 months ago
Product Engineering & Quality

$180,770 - $255,200 USD yearly

Originally posted 25 August 2026 by the employer.

Support development of Hybrid Bond Interconnect (HBI) and Embedded Multi-die Interconnect Bridge (EMIB-T) packaging technologies.

About the role

As the Stress Test and Reliability (STaR) Back-End Laboratory Manager, you will play a critical leadership role within the Foundry Lab Network (FLN) at Intel.

What you'll do

  • Manage, hire, coach, and develop a team of 8-10 laboratory engineers.
  • Define and execute the laboratory capability and capacity roadmap.
  • Ensure timely and effective response to internal and external customer needs.
  • Develop and implement a comprehensive strategy to support data collection and qualification requirements for emerging packaging technologies.
  • Establish and advance Reliability Quick Turn Monitoring (QTM) methodologies.
  • Lead the laboratory's quality management system development and readiness efforts to achieve ISO 17025 accreditation.

What you'll need

  • Master's degree in Electrical Engineering, Mechanical Engineering, Physics, Materials Science, or a related technical discipline.
  • 3+ years of engineering management experience in semiconductor packaging, reliability engineering, test engineering, or validation engineering.
  • Demonstrated expertise in process qualification, reliability risk assessment, quality management systems, and quality culture development.
  • 2+ years of experience in hands-on reliability stress and testing.

Nice to have

  • Experience with dynamics testing, especially including shock and vibration, to JEDEC or other standards-based requirements.
  • Experience with industry standard stress requirements, especially those contained within JESD47 requirements.
  • Knowledge of advanced packaging assembly process and modules, preferably with experience in design rule scaling and/or defect failure modes.
  • Experience with coordination and auditing of third-party stress labs.

Skills: packaging technologies, reliability engineering, stress test, quality management systems, ISO 17025

Market context

This role has been open 51 days — below the 57-day median for Reliability Engineering roles.

Reliability Engineering · Reliability Engineering

Open roles in category
425
Median days open
57 d
Median salary
$158k
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
How Intel Corporation compares in Reliability Engineering hiring
Metric Intel Corporation All employers we track in this specialty (425 roles · 70 employers)
Open roles in this specialty 17 425
Open roles in the wider Process, Fab & Equipment family 187 9867 · 109 employers
Median days open 35 d 57 d (−22 d vs this employer)
Median salary (USD postings) — $158k

Skills observed across this category: packaging technologies, reliability engineering, stress test, quality management systems, ISO 17025

Who's hiring in this category

  • Micron Technology · 75 open roles · median 146 d
  • Infineon Technologies · 32 open roles · median 49 d
  • Renesas Electronics · 20 open roles · median 41 d
  • Intel Corporation (this employer) · 19 open roles · median 35 d
  • Analog Devices · 18 open roles · median 55 d
  • onsemi · 18 open roles · median 73 d

How we counted: 425 open Reliability Engineering (Reliability Engineering) roles from 70 employers tracked in the SemiconductorJobs index, counted 15 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Process, Fab & Equipment family row. Figures refresh nightly.

Apply now
US, Arizona, Phoenix, United States
On-site
$180,770 - $255,200 USD yearly
2 months ago

Share this job