$121,900 USD yearly
Drive yield optimization, quality assurance, and RMA failure analysis for XPU ASICs on Advantest 93K platforms.
Originally posted 9 November 2026 by the employer.
About the role
This role drives testing, yield optimization, quality assurance, and RMA failure analysis for high-performance XPU ASIC parts spanning monolithic and 2.5D/3D advanced packaging. Testing is performed on Advantest PS1600, PS400B UHC4, and 93K PinScale/Exascale testers.
What you'll do
- Execute test bring-up, silicon characterization, flow development, and test time optimization for XPU devices on ATE platforms.
- Develop and deploy robust ATE test solution recipes and patterns for product silicon.
- Perform ATE test data analysis, shmoo characterizations, and guardband tuning to drive silicon yield improvements and reduce DPPM.
- Execute ASIC/XPU temperature and voltage corner testing to ensure product quality and screening efficacy.
- Lead characterization, fault isolation, and root-cause debug of customer RMA parts across monolithic and 2.5D/3D advanced packaging XPUs.
- Manage ATE testing for pre- and post-reliability and environmental stress testing, oversee test file revision control, and maintain DUT hardware and load boards.
What you'll need
- BS or MS in Electrical or Computer Engineering with a background in ASIC/XPU ATE testing, especially with Advantest 93K systems.
- Minimum 8+ years of experience in test development, yield enhancement, and RMA failure analysis on ATE floors.
- Demonstrated experience testing complex ASIC/XPU parts in monolithic and 2.5D packaging.
- Strong software/scripting skills and familiarity with Linux RedHat and SmarTest (e.g., versions 7.x, 8.x).
- Proven debug and root cause analysis capabilities.
More semiconductor jobs: Broadcom jobs · Test engineer jobs
This role has been open 0 days — well below the 40-day median for Silicon Test Engineering roles.
Silicon Test Engineering · DFT Test
|
Open roles in category
639
|
Median days open
40 d
|
Category median salary (all employers)
$176k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Broadcom | All employers we track in this specialty (639 roles · 86 employers) |
|---|---|---|
| Open roles in this specialty | 11 | 639 |
| Open roles in the wider Silicon Validation & Test family | 23 | 2401 · 121 employers |
| Median days open | 13 d | 40 d (−27 d vs this employer) |
| Median salary (USD postings) | — | $176k |
Who's hiring in this category
- Teradyne · 83 open roles · median 38 d
- Infineon Technologies · 51 open roles · median 35 d
- Renesas Electronics · 45 open roles · median 34 d
- Texas Instruments · 33 open roles · median 45 d
- Qualcomm · 29 open roles · median 52 d
- Micron Technology · 25 open roles · median 56 d
How we counted: 639 open Silicon Test Engineering (DFT Test) roles from 86 employers tracked in the SemiconductorJobs index, counted 9 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Silicon Validation & Test family row. Figures refresh nightly.