ASICS Design Verification Engineer-Senior to Staff
$121,800 - $182,600 USD yearly
Originally posted 23 October 2026 by the employer.
About the role
This role covers the complete verification lifecycle from system-level concept to tape out and post-silicon support. The scope involves pre-silicon test planning, testbench development using SystemVerilog-UVM, coverage closure, assertion modeling, and formal verification for digital power IPs.
What you'll do
- Execute comprehensive pre-silicon test planning for digital power IPs. - Develop testbenches using verification methodologies including SystemVerilog-UVM. - Implement coverage development, assertion model development, and formal verification property checking. - Learn and deploy power-aware UPF verification flows and methodologies. - Build automation scripts to enhance verification efficiency.
What you'll need
- Bachelor's degree in Science, Engineering, or a related field with 2+ years of ASIC design, verification, validation, integration, or related experience (or Master's degree with 1+ year, or PhD). - 2 years of experience with ASIC design and verification tools, techniques, and methodology.
Nice to have
- Master’s degree in Computer Science, Electrical Engineering, Computer Engineering, or a closely related field. - 6 years of experience with ASIC design and verification tools, techniques, and methodology. - 6 years of experience with digital design concepts and RTL languages such as SystemVerilog, Verilog, or VHDL. - 6 years of experience with computer architecture fundamentals, object-oriented programming concepts, and C or C++ programming. - 6 years of experience developing block-level testbench environments using SystemVerilog. - 6 years of experience with verification methodologies such as UVM or OVM and exposure to assertion-based formal verification. - 6 years of experience with scripting and automation using Perl or Python. - Experience with AMBA bus protocols such as AXI, AHB, or APB. - Knowledge or experience with assertion-based formal verification.
Skills: ASIC, UVM, SystemVerilog, RTL, Testbench
This role has been open 0 days — well below the 65-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1241
|
Median days open
65 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (1241 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 120 | 1241 |
| Open roles in the wider Digital Design & Verification family | 423 | 3322 · 115 employers |
| Median days open | 42 d | 65 d (−23 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: ASIC, UVM, SystemVerilog, RTL, Testbench
Who's hiring in this category
- Qualcomm (this employer) · 115 open roles · median 42 d
- AMD · 94 open roles · median 52 d
- NVIDIA · 85 open roles · median 64 d
- Synopsys · 66 open roles · median 38 d
- SiFive · 55 open roles · median 80 d
- Cadence Design Systems · 52 open roles · median 122 d
How we counted: 1241 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 23 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.