$100,000 - $189,750 USD yearly
Originally posted 28 September 2026 by the employer.
About the role
This role is for an ASIC Verification Engineer focused on verifying the Memory Management Unit of GPUs.
What you'll do
- Understand the design and implementation with a focus on the Memory Management Unit.
- Define the verification scope.
- Develop the verification infrastructure (Testbenches, BFMs, Checkers, Monitors).
- Implement test/coverage plans.
- Verify the correctness of the design.
- Plan and work on the strategic direction of the methodology for the testbench with advanced methodology.
What you'll need
- BS or MS in Electrical Engineering, Computer Science, Computer Engineering or related field.
- Exposure to Computer Architecture, ASIC design and verification methodology.
- Proficiency with SystemVerilog, C and/or C++, test planning, coverage closure, and creating reusable verification components.
- Knowledgeable in constrained random testing with functional coverage and assertion-based verification.
- Understanding of object-oriented programming concepts.
- Exposure to simulation tools like VCS, IES and debug tools like Debussy, GDB.
Skills: Verification Engineer, Memory Management Unit, SystemVerilog, test/coverage plans, UVM
More semiconductor jobs: NVIDIA jobs · Verification engineer jobs
First seen in our index 45 days ago, well below the 59-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1412
|
Median days since first seen
59 d
|
Category median salary (all employers)
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | NVIDIA | All employers we track in this specialty (1412 roles · 101 employers) |
|---|---|---|
| Open roles in this specialty | 109 | 1412 |
| Open roles in the wider Digital Design & Verification family | 290 | 3617 · 122 employers |
| Median days since first seen | 73 d | 59 d (−14 d vs this employer) |
| Median salary (USD postings) | n/a | $185k |
Skills observed across this category: Verification Engineer, Memory Management Unit, SystemVerilog, test/coverage plans, UVM
Who's hiring in this category
- Qualcomm · 138 open roles · median 52 d
- NVIDIA (this employer) · 109 open roles · median 74 d
- Apple · 107 open roles · median 17 d
- Synopsys · 90 open roles · median 53 d
- AMD · 81 open roles · median 65 d
- SiFive · 57 open roles · median 72 d
How we counted: 1412 open Design Verification (Design Verification) roles from 101 employers tracked in the SemiconductorJobs index, counted 14 Nov 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there, and is counted in the wider Digital Design & Verification family row. Days are counted from when our index first saw each posting, not from the employer's original posting date.