ASIC II - AMZ27538.3 - Cupertino, California, United States
$157,300 - $212,800 USD yearly
Originally posted 9 September 2026 by the employer.
About the role
This role involves designing and optimizing hardware in data centers, including AWS Inferentia.
What you'll do
- Develop and implement high-performance, area and power-efficient RTL designs.
- Conduct in-depth analysis of designs, microarchitectures, and architectures to optimize trade-offs.
- Create microarchitectures, implement SystemVerilog RTL, and deliver synthesis and timing-clean designs.
- Execute lint and clock domain crossing quality checks to ensure design integrity.
- Collaborate with architects, fellow designers, verification specialists, and pre- and post-silicon validation teams.
What you'll need
- Experience designing and optimizing hardware in data centers.
- Experience developing and implementing RTL designs.
- Expertise in microarchitectures.
- Proficiency in SystemVerilog RTL.
- Knowledge of synthesis and timing-clean designs.
- Ability to execute lint and clock domain crossing quality checks.
Skills: microarchitectures, SystemVerilog RTL, synthesis, timing-clean designs, lint, clock domain crossing
This role has been open 30 days — well below the 61-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1021
|
Median days open
61 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Amazon | All employers we track in this specialty (1021 roles · 103 employers) |
|---|---|---|
| Open roles in this specialty | 12 | 1021 |
| Open roles in the wider Digital Design & Verification family | 28 | 3191 · 115 employers |
| Median days open | 30 d | 61 d (−31 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: microarchitectures, SystemVerilog RTL, synthesis, timing-clean designs, lint, clock domain crossing
Who's hiring in this category
- Qualcomm · 134 open roles · median 64 d
- Synopsys · 86 open roles · median 29 d
- AMD · 72 open roles · median 35 d
- Analog Devices · 49 open roles · median 47 d
- NVIDIA · 46 open roles · median 63 d
- NXP Semiconductors · 41 open roles · median 84 d
How we counted: 1021 open Digital/RTL Design (RTL Design) roles from 103 employers tracked in the SemiconductorJobs index, counted 15 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.