ASIC Engineer Intern, Annapurna Labs - 2027 - Cupertino, California, United States
Originally posted 27 August 2026 by the employer.
Annapurna Labs designs custom silicon including Graviton, Trainium, Inferentia, and the Nitro system.
About the role
As an ASIC Engineer Intern, you will contribute to real chip development work at Annapurna Labs, designing custom silicon for server processors, machine learning accelerators, and the Nitro system.
What you'll do
- Design and implement RTL for digital logic blocks using Verilog/SystemVerilog - Develop and run verification environments to validate design functionality and coverage - Support synthesis, timing analysis, and physical design flows - Debug design issues through simulation and analysis - Collaborate with architecture, verification, and physical design teams - Document design decisions and present work to the team
What you'll need
- Experience with RTL design for digital logic blocks - Familiarity with Verilog/SystemVerilog - Understanding of design functionality and coverage - Knowledge of synthesis, timing analysis, and physical design flows - Ability to debug design issues through simulation and analysis - Collaboration with architecture, verification, and physical design teams
Skills: RTL design, Verilog/SystemVerilog, digital logic blocks, design functionality, SoC integration
This role has been open 49 days — well below the 61-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1021
|
Median days open
61 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Amazon | All employers we track in this specialty (1021 roles · 103 employers) |
|---|---|---|
| Open roles in this specialty | 11 | 1021 |
| Open roles in the wider Digital Design & Verification family | 27 | 3183 · 115 employers |
| Median days open | 30 d | 61 d (−31 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: RTL design, Verilog/SystemVerilog, digital logic blocks, design functionality, SoC integration
Who's hiring in this category
- Qualcomm · 134 open roles · median 64 d
- Synopsys · 86 open roles · median 29 d
- AMD · 72 open roles · median 35 d
- Analog Devices · 49 open roles · median 47 d
- NVIDIA · 46 open roles · median 63 d
- NXP Semiconductors · 41 open roles · median 84 d
How we counted: 1021 open Digital/RTL Design (RTL Design) roles from 103 employers tracked in the SemiconductorJobs index, counted 15 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.
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