ASIC Design Verification Engineer (Security Group) - Sr Staff
$190,200 - $285,400 USD yearly
Originally posted 23 October 2026 by the employer.
About the role
As a Design Verification Engineer, you will work with Chip Architects to validate core and sub-system level micro-architectures for secure subsystem designs.
What you'll do
- Develop detailed test and coverage plans based on subsystem architecture and micro-architecture. - Develop verification environments, testbenches, and components including stimulus, checkers, monitors, assertions, and coverpoints. - Execute verification plans across design bring-up, DV environment bring-up, regression suites, and debug of test failures. - Run and analyze coverage reports, identify coverage holes, and update test plans to achieve coverage metrics. - Write technical documentation including feature descriptions, architectural descriptions, and verification test plans, and review documentation from junior engineers. - Collaborate with subsystem and SOC architects to define requirements, review test plans, and resolve debug issues.
What you'll need
- Bachelor's degree in Science, Engineering, or a related field with 6+ years of ASIC design or verification experience (or Master's with 5+ years, or PhD with 4+ years). - Experience in SOC-level verification with debugging of ARM-based or RISC-V based processors. - Understanding of APB, AHB, and AXI protocols. - Hands-on expertise with SystemVerilog and UVM concepts. - Experience with Synopsys VCS and Verdi. - Proficiency in Python or Perl scripting, UNIX commands, and Makefile automation. - Practical experience with assertion-based verification and functional coverage.
Nice to have
- Prior experience in cryptographic algorithms. - Deep knowledge of APB, AXI, and SPI protocols, handshake mechanisms, cross-clock domains, and clock gating. - Understanding of memory organization, fault-tolerant design, parity schemes, and error detection and correction schemes. - Experience with formal verification, gate-level simulation, and silicon bring-up. - In-depth knowledge of microprocessor functions, Network-on-Chip architectures, and micro-architectures. - Experience writing portable testbenches, transactors, and assembly code.
Skills: UVM, SystemVerilog, ASIC, VCS, Coverage, Security
This role has been open 0 days — well below the 65-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1241
|
Median days open
65 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (1241 roles · 97 employers) |
|---|---|---|
| Open roles in this specialty | 120 | 1241 |
| Open roles in the wider Digital Design & Verification family | 423 | 3322 · 115 employers |
| Median days open | 42 d | 65 d (−23 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: UVM, SystemVerilog, ASIC, VCS, Coverage, Security
Who's hiring in this category
- Qualcomm (this employer) · 115 open roles · median 42 d
- AMD · 94 open roles · median 52 d
- NVIDIA · 85 open roles · median 64 d
- Synopsys · 66 open roles · median 38 d
- SiFive · 55 open roles · median 80 d
- Cadence Design Systems · 52 open roles · median 122 d
How we counted: 1241 open Design Verification (Design Verification) roles from 97 employers tracked in the SemiconductorJobs index, counted 23 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.