ASIC Design Engineer – SoC Interconnect, Cache & Memory Systems
$101,400 - $152,200 USD yearly
Originally posted 22 October 2026 by the employer.
Design RTL for SoC interconnects, cache controllers, and high-speed DDR memory controllers.
About the role
This role contributes to the architecture, microarchitecture, design, and deployment of SoC interconnects, cache and memory subsystems, and DDR memory controllers. You will collaborate with verification, physical design, and software teams to deliver silicon solutions for smartphones, PCs, XR devices, and automotive platforms.
What you'll do
- Develop microarchitecture definitions and design specifications for complex SoC subsystems. - Design, implement, and validate RTL for SoC interconnects, cache controllers, memory subsystems, and DDR memory controller components. - Optimize designs for performance, power, area, timing, and scalability while collaborating with system architects. - Support synthesis, timing closure, power analysis, gate-level simulations, and physical design activities. - Work closely with verification teams to develop test plans, review coverage, debug issues, and resolve pre-silicon and post-silicon bugs. - Contribute to C/C++ modeling, design methodologies, and process improvements.
What you'll need
- Bachelor's degree in Science, Engineering, Electrical Engineering, Computer Engineering, Computer Science, or a related field. - 0-4 years of industry experience or relevant academic experience in ASIC/SoC design. - Experience or coursework in Verilog and/or SystemVerilog RTL design. - Experience or coursework in computer architecture and digital logic design. - Experience or coursework in C, C++, and/or Python programming.
Nice to have
- Experience or knowledge in SoC interconnects and on-chip communication fabrics. - Experience or knowledge in cache and memory subsystem design, or DDR/LPDDR memory controller architecture and design. - Knowledge of ARM or x86 processor architectures and bus protocols. - Experience with low-power design methodologies and coverage-driven verification techniques. - Familiarity with Synopsys synthesis tools, ASIC implementation flows, timing closure, silicon bring-up, and post-silicon debug.
Skills: RTL, SystemVerilog, SoC Interconnect, Cache Controller, DDR
This role has been open 0 days — well below the 63-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1078
|
Median days open
63 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Qualcomm | All employers we track in this specialty (1078 roles · 103 employers) |
|---|---|---|
| Open roles in this specialty | 160 | 1078 |
| Open roles in the wider Digital Design & Verification family | 423 | 3322 · 115 employers |
| Median days open | 59 d | 63 d (−4 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: RTL, SystemVerilog, SoC Interconnect, Cache Controller, DDR
Who's hiring in this category
- Qualcomm (this employer) · 157 open roles · median 59 d
- Synopsys · 88 open roles · median 36 d
- AMD · 76 open roles · median 41 d
- Analog Devices · 49 open roles · median 52 d
- NXP Semiconductors · 42 open roles · median 91 d
- NVIDIA · 40 open roles · median 63 d
How we counted: 1078 open Digital/RTL Design (RTL Design) roles from 103 employers tracked in the SemiconductorJobs index, counted 23 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.