ASIC Design Engineer - Hardware - TX, Austin, United States
$116,000 - $218,500 USD yearly
Originally posted 8 October 2026 by the employer.
About the role
As an ASIC Design Engineer in the System-On-Chip (SOC) group, you will focus on improving methodologies and delivering system-level IP to measure performance across multiple projects.
What you'll do
- Define, develop, and deliver system-level methodologies and RTL to measure performance on GPUs and SOCs. - Define, develop, and automate flows and methodologies to build, deliver, and support system-level IP. - Deliver IP and support projects by applying performance monitoring systems. - Run and debug RTL checks to ensure design quality, covering cross clock domains (CDC), clocks, resets, latency, and related metrics. - Design and implement RTL features across microarchitecture and RTL implementation. - Collaborate with architects, designers, and software engineers to accomplish engineering tasks.
What you'll need
- BS or equivalent experience in Electrical Engineering, Computer Engineering, or a related field. - 2+ years of relevant industry experience and coding skills in Perl, Python, or other industry-standard scripting languages. - Experience in RTL design (Verilog), verification (SystemVerilog), System-On-Chip design/implementation flow, and design automation. - Understanding of SOC architecture, including CDC, multiple-power domains, performance analysis, latency, and data flow. - Exposure to design and verification tools such as dc_shell or equivalent synthesis tools, VCS or equivalent simulation tools, and debug tools like Debussy or GDB.
Nice to have
- Advanced degrees (MS, PhD). - Hands-on experience in object-oriented programming. - Prior design experience with system-level IP (Clocks/DFT/Resets). - Experience developing methodologies used by others. - Hands-on silicon debug experience. - Exposure to physical design.
Skills: RTL, Verilog, System-On-Chip design, SOC architecture, CDC
This role has been open 132 days — well above the 63-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1078
|
Median days open
63 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | NVIDIA | All employers we track in this specialty (1078 roles · 103 employers) |
|---|---|---|
| Open roles in this specialty | 39 | 1078 |
| Open roles in the wider Digital Design & Verification family | 225 | 3322 · 115 employers |
| Median days open | 63 d | 63 d (same as this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: RTL, Verilog, System-On-Chip design, SOC architecture, CDC
Who's hiring in this category
- Qualcomm · 157 open roles · median 59 d
- Synopsys · 88 open roles · median 36 d
- AMD · 76 open roles · median 41 d
- Analog Devices · 49 open roles · median 52 d
- NXP Semiconductors · 42 open roles · median 91 d
- NVIDIA (this employer) · 40 open roles · median 63 d
How we counted: 1078 open Digital/RTL Design (RTL Design) roles from 103 employers tracked in the SemiconductorJobs index, counted 23 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.