ASIC Design Engineer – Fabric/Interconnect - Austin, United States
Originally posted 12 October 2026 by the employer.
About the role
This role involves the design and integration of coherent and non-coherent fabrics into a subsystem or SoC, with a focus on on-chip interconnect architectures.
What you'll do
- Design and integrate coherent and non-coherent fabrics into a subsystem or SoC. - Own all aspects of RTL development, including design, templating, scripting, and RTL generation. - Integrate common/shared IP blocks to design and optimize memories/hard macros for the block. - Work with front-end synthesis/STA teams to ensure timing for the block is met. - Collaborate with power/performance and functional verification teams to ensure high quality of the block. - Work with multi-disciplinary groups to ensure designs are delivered on time with high quality.
What you'll need
- BS degree with 0 years of relevant industry experience.
Nice to have
- Knowledge of cache coherency protocols (MESI, MOESI, directory-based coherence) and memory hierarchy. - Experience delivering large, sophisticated designs in high volume production for low power applications. - Working experience with synthesis, power, performance, and verification teams to deliver high quality RTL design. - Familiarity with front-end tools including lint, CDC, and synthesis.
Skills: RTL development, interconnect architectures, NoC topologies, cache coherency, synthesis
This role has been open 2 days — well below the 61-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
1021
|
Median days open
61 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Apple | All employers we track in this specialty (1021 roles · 103 employers) |
|---|---|---|
| Open roles in this specialty | 9 | 1021 |
| Open roles in the wider Digital Design & Verification family | 64 | 3191 · 115 employers |
| Median days open | 4 d | 61 d (−57 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: RTL development, interconnect architectures, NoC topologies, cache coherency, synthesis
Who's hiring in this category
- Qualcomm · 134 open roles · median 64 d
- Synopsys · 86 open roles · median 29 d
- AMD · 72 open roles · median 35 d
- Analog Devices · 49 open roles · median 47 d
- NVIDIA · 46 open roles · median 63 d
- NXP Semiconductors · 41 open roles · median 84 d
How we counted: 1021 open Digital/RTL Design (RTL Design) roles from 103 employers tracked in the SemiconductorJobs index, counted 15 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.