ASIC Design Engineer - Digital DSP Design & Analog/Mixed-Signal - Ottawa, Ontario, Canada
Originally posted 22 August 2026 by the employer.
About the role
This role involves designing and implementing advanced ASICs for high-speed optical communication systems. The position focuses on integrating DSP, Analog, and SerDes technologies into complex ASIC designs.
What you'll do
- Design and implement high-performance digital circuits and ASIC blocks using Verilog and SystemVerilog.
- Develop and integrate DSP, digital communication, and high-speed SerDes functionality into complex ASIC designs.
- Work closely with Analog, SerDes, DSP, Architecture, Verification, Physical Design, and Systems teams to develop and integrate mixed-signal ASICs.
- Perform synthesis, timing analysis, lint, formal equivalence, Clock Domain Crossing (CDC), and related ASIC implementation and signoff activities.
- Optimize designs for performance, power, and area (PPA).
- Perform RTL simulation and debugging to ensure design functionality and performance.
What you'll need
- 5+ years of experience in digital ASIC design, with demonstrated ownership of complex ASIC blocks or subsystems.
- Strong proficiency in Verilog and/or SystemVerilog.
- Strong understanding of digital design principles, RTL design, and ASIC development methodologies.
- Hands-on experience with ASIC design flows and industry-standard EDA tools.
- Strong knowledge of one or more of the following areas: Digital Signal Processing (DSP), High-speed SerDes, Analog/Mixed-Signal ICs, Digital communications, Optical communications.
- Experience working with DSP algorithms, data-path architectures, FEC, equalization, modulation/demodulation, or other high-speed communication technologies.
- Understanding of SerDes architectures and high-speed interfaces, including TX/RX datapaths, equalization, clocking, and related mixed-signal interfaces.
- Experience collaborating with Analog and Mixed-Signal design teams and understanding the interaction between digital, analog, and SerDes blocks.
- Experience with synthesis, static timing analysis, Lint, CDC, formal verification, and RTL simulation.
- Familiarity with verification methodologies such as UVM and/or formal verification.
- Knowledge of low-power design techniques and PPA optimization.
Nice to have
- Experience designing ASICs for optical communications, optical transceivers, coherent communications, or high-speed networking.
- Experience with coherent DSP, FEC, modulation schemes, equalization, or high-speed data recovery.
- Experience with SerDes architectures, including TX/RX, CDR, PLLs, CTLE, DFE, ADC/DAC interfaces, or related high-speed mixed-signal circuitry.
- Experience working with advanced semiconductor process technologies.
- Experience taking ASICs from architecture/RTL through synthesis, physical implementation, tapeout, and silicon bring-up.
- Experience with MATLAB, Python, Tcl, or other modeling and automation tools.
- Understanding of optical communication standards and high-speed networking protocols.
Skills: Verilog, SystemVerilog, DSP, SerDes, ASIC design
This role has been open 65 days — well below the 96-day median for Digital/RTL Design roles.
Digital/RTL Design · Mixed Signal DSP
|
Open roles in category
33
|
Median days open
96 d
|
Median salary
$192k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Celero | All employers we track in this specialty (33 roles · 18 employers) |
|---|---|---|
| Open roles in this specialty | 5 | 33 |
| Open roles in the wider Digital Design & Verification family | 8 | 3328 · 116 employers |
| Median days open | 5 d | 96 d (−91 d vs this employer) |
| Median salary (USD postings) | — | $192k |
Skills observed across this category: Verilog, SystemVerilog, DSP, SerDes, ASIC design
Who's hiring in this category
- Celero (this employer) · 5 open roles · median 5 d
- Infineon Technologies · 4 open roles · median 51 d
- Keysight Technologies · 4 open roles · median 119 d
- Altera · 2 open roles · median 37 d
- Marvell Technology · 2 open roles · median 157 d
- NXP Semiconductors · 2 open roles · median 126 d
How we counted: 33 open Digital/RTL Design (Mixed Signal DSP) roles from 18 employers tracked in the SemiconductorJobs index, counted 27 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.