ASIC Design Engineer - Digital DSP Design & Analog/Mixed-Signal - Irvine, CA, United States
Celero
Irvine, CA, United States
1 month ago
Digital Design & SoC Architecture
$150,000 - $250,000 USD yearly
Originally posted 22 August 2026 by the employer — open 19 days.
About the role
This role involves designing and developing advanced ASICs for high-speed optical communication systems.
What you'll do
- Design and implement high-performance digital circuits and ASIC blocks using Verilog and SystemVerilog.
- Develop and integrate DSP, digital communication, and high-speed SerDes functionality into complex ASIC designs.
- Collaborate with Analog, SerDes, DSP, Architecture, Verification, Physical Design, and Systems teams to develop and integrate mixed-signal ASICs.
- Perform synthesis, timing analysis, lint, formal equivalence, Clock Domain Crossing (CDC), and related ASIC implementation and signoff activities.
- Optimize designs for performance, power, and area (PPA).
- Develop scripts and automation using Python, Tcl, or similar languages to improve design and verification efficiency.
What you'll need
- 5+ years of experience in digital ASIC design, with demonstrated ownership of complex ASIC blocks or subsystems.
- Strong proficiency in Verilog and/or SystemVerilog.
- Strong understanding of digital design principles, RTL design, and ASIC development methodologies.
- Hands-on experience with ASIC design flows and industry-standard EDA tools.
- Strong knowledge of one or more of Digital Signal Processing (DSP), High-speed SerDes, Analog/Mixed-Signal ICs, Digital communications, or Optical communications.
- Experience with synthesis, static timing analysis, Lint, CDC, formal verification, and RTL simulation.
- Familiarity with verification methodologies such as UVM and/or formal verification.
Nice to have
- Experience designing ASICs for optical communications, optical transceivers, coherent communications, or high-speed networking.
- Experience with coherent DSP, FEC, modulation schemes, equalization, or high-speed data recovery.
- Experience with SerDes architectures, including TX/RX, CDR, PLLs, CTLE, DFE, ADC/DAC interfaces, or related high-speed mixed-signal circuitry.
- Experience taking ASICs from architecture/RTL through synthesis, physical implementation, tapeout, and silicon bring-up.
- Experience with MATLAB, Python, Tcl, or other modeling and automation tools.
- Understanding of optical communication standards and high-speed networking protocols.
Market context
This role has been open 19 days — well below the 63-day median for Digital/RTL Design roles.
Digital/RTL Design · RTL Design
|
Open roles in category
935
|
Median days open
63 d
|
Median salary
$182k
|
See the full market breakdown ▾Category comparison, and who else is hiring
| Metric | Celero | All employers we track in this specialty (935 roles · 101 employers) |
|---|---|---|
| Open roles in this specialty | 2 | 935 |
| Open roles in the wider Digital Design & Verification family | 4 | 3055 · 116 employers |
| Median days open | 87 d | 63 d (+24 d vs this employer) |
| Median salary (USD postings) | — | $182k |
Who's hiring in this category
- Qualcomm · 133 open roles · median 53 d
- AMD · 56 open roles · median 65 d
- NXP Semiconductors · 52 open roles · median 60 d
- NVIDIA · 50 open roles · median 47 d
- Synopsys · 43 open roles · median 77 d
- Marvell Technology · 40 open roles · median 118 d
How we counted: 935 open Digital/RTL Design (RTL Design) roles from 101 employers tracked in the SemiconductorJobs index, counted 11 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.
Celero
Irvine, CA, United States
On-site
$150,000 - $250,000 USD yearly
1 month ago