Architecture Intern, MS - Summer 2027 - Burlington, VT, United States
$31 - $62 USD yearly
Originally posted 28 September 2026 by the employer.
Work on architecture for datacenter products.
About the role
This role is for an ASIC architect/engineering intern to join the architecture team, acting as the central technical interface to datacenter clients. This team is responsible for overall technology choice, silicon partitioning strategy, IP definition and selection, and architectural guidance of datacenter products (SmartNIC, servers, AI accelerators, and switches).
What you'll do
- Engage with customers, engineering, and marketing to help define chip architectures of innovative and complex datacenter products. - Identify the best silicon partitioning, IP selection, and packaging technology. - Map Marvell solutions into highly effective presentations and share with customers. - Communicate and coordinate with other business units in Marvell on internal IP and sharing/leveraging capabilities and knowledge. - Document findings and present results to the team.
What you'll need
- Currently pursuing a Master’s Degree in Electrical Engineering, Computer Engineering, or a related field with an expected graduation date between Fall 2027 – Summer 2028. - Knowledge of system architectures for datacenter products. - Knowledge of CMOS technology. - Knowledge of physical design flow.
Nice to have
- Strong programming experience and knowledge.
Skills: ASIC architect, chip architectures, silicon partitioning strategy, IP definition, datacenter products
This role has been open 1 day — well below the 73-day median for SoC/Chip Architecture roles.
SoC/Chip Architecture · SOC Architecture
|
Open roles in category
436
|
Median days open
73 d
|
Median salary
$237k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Marvell Technology | All employers we track in this specialty (436 roles · 64 employers) |
|---|---|---|
| Open roles in this specialty | 6 | 436 |
| Open roles in the wider Digital Design & Verification family | 31 | 3105 · 115 employers |
| Median days open | 24 d | 73 d (−49 d vs this employer) |
| Median salary (USD postings) | — | $237k |
Skills observed across this category: ASIC architect, chip architectures, silicon partitioning strategy, IP definition, datacenter products
Who's hiring in this category
- Qualcomm · 73 open roles · median 77 d
- NVIDIA · 59 open roles · median 54 d
- AMD · 36 open roles · median 72 d
- Arm Holdings · 27 open roles · median 97 d
- NXP Semiconductors · 19 open roles · median 99 d
- Renesas Electronics · 17 open roles · median 99 d
How we counted: 436 open SoC/Chip Architecture (SOC Architecture) roles from 64 employers tracked in the SemiconductorJobs index, counted 30 Sept 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.