Applied ML – Functional Verification Engineer - San Jose, United States
$114,800 - $213,200 USD yearly
Originally posted 6 March 2026 by the employer.
Join the ChipStack AI Super Agent team applying agentic AI platforms and LLMs to pre-silicon functional verification.
About the role
Cadence Design Systems is seeking a Pre-Silicon Verification Engineer with experience in functional verification to join the ChipStack AI Super Agent team. In this role, you will apply machine learning techniques and agentic AI platforms to pre-silicon design and verification lifecycles.
What you'll do
- Apply machine learning techniques to streamline pre-silicon functional verification methodologies including formal verification and UVM. - Develop agentic AI solutions using LLMs and machine learning technologies to support pre-silicon design verification processes. - Employ AI enhanced Electronic Design Automation (EDA) tools to assist design and verification lifecycles. - Engage directly with customers to evaluate requirements and deliver verification strategies. - Collaborate with machine learning and software engineering teams to validate output correctness, efficiency, and quality. - Track technical advancements in AI-powered hardware verification and share technical knowledge across teams.
What you'll need
- BS with a minimum of 4 years of experience, MS with a minimum of 2 years of experience, or a new PhD graduate. - More than 3 years of experience in pre-silicon ASIC verification methodologies such as Formal, SV/UVM, or OVM. - Advanced skills in debugging pre-silicon verification failures using waveform viewers and simulation analysis tools. - Hands-on experience with EDA tools including Jasper, Xcelium, or IMC. - Strong programming skills in Verilog, System Verilog, and Python.
Nice to have
- Exposure to LLMs and ML technologies such as RAG, RFT, RL, and Agentic frameworks.
Skills: functional verification, formal verification, UVM, simulation, AI enhanced EDA tools
This role has been open 215 days — well above the 67-day median for Design Verification roles.
Design Verification · Design Verification
|
Open roles in category
1268
|
Median days open
67 d
|
Median salary
$185k
|
See the full market breakdown ▾Category comparison, skills in demand, and who else is hiring
| Metric | Cadence Design Systems | All employers we track in this specialty (1268 roles · 96 employers) |
|---|---|---|
| Open roles in this specialty | 50 | 1268 |
| Open roles in the wider Digital Design & Verification family | 121 | 3346 · 116 employers |
| Median days open | 131 d | 67 d (+64 d vs this employer) |
| Median salary (USD postings) | — | $185k |
Skills observed across this category: functional verification, formal verification, UVM, simulation, AI enhanced EDA tools
Who's hiring in this category
- Qualcomm · 120 open roles · median 46 d
- NVIDIA · 93 open roles · median 66 d
- AMD · 92 open roles · median 56 d
- Synopsys · 67 open roles · median 42 d
- SiFive · 56 open roles · median 80 d
- Cadence Design Systems (this employer) · 50 open roles · median 132 d
How we counted: 1268 open Design Verification (Design Verification) roles from 96 employers tracked in the SemiconductorJobs index, counted 27 Oct 2026. Specialty figures count only roles carrying this exact specialty label, so an employer's related work in neighbouring specialties is not included there — it is counted in the wider Digital Design & Verification family row. Figures refresh nightly.